Exo said:
If your timer circuit starts clocking 8 times right after the startbit and then stops then your shift register will have read the 8 databits, no incorrect bits will be read...
Erm..what i need to know is the
output of the serial shift register. :?
How am i going to take the correct parallel bits out of the serial data? :?:
If 1011 0110 --> going into the shift register,
At first clock pulse, the SIPO output will be 0xxx xxxx.(where x is an unknow state)
At second clock pulse, parallel output is 10xx xxxx.
At third clock pulse, parallel output is 110x xxxx.
At fourth clock pulse, parallel output is 0110 xxxx.
.....
.....
At eighth clock pulse, parallel output is 1011 0110.
Agree with those?? :roll:
So if i want to make 1011 0110 parallel output available at the dot matrix array, what should i do to prevent those previous 7 incorrect parallel bits from entering the dot matrix column? Is it there should be a 'special' circuit that only allow the correct parallel bits to go through?? Will a D latch do the job?
I apologise if i have offended you. :cry: