Problems with CPLD programmer

[Snowman]

Hi,

I'm using the following parallel port programmer cable:
**broken link removed**

I've implemented this circuit and have setup a 44pin plcc socket to test on. I'm using "iMPACT" software which is part of the latest WebPack ISE package given away for free on the Xilinx site. The software seems to recognise something is connected:

Connecting to cable (Parallel Port - LPT2).
Checking cable driver.
Driver windrvr.sys version = 5.0.5.1.
LPT base address = 0378h.
Cable connection established.


Then, when I proceed to attempt a chain init, it prints:

Identifying chain contents ....
'1': : Manufacturer's ID =Unknown
INFO:iMPACT:501 - '1': Added Device UNKNOWN successfully.
----------------------------------------------------------------------

...and continues infinitely, incrementing the device # each time.


I'm not sure what's wrong with the circuit or software or what I'm doing...if anyone has had previous experience with this - please help

 

[kinjalgp]

What is the length of your Parallel Port Cable?

 

[Snowman]

Less than 2m - I think that's the limit....

 

[eemage21]

cpld

are you using a xillinx cpld? Device ID is located on the chip. Either that, or you've got incompatible cable.

 

[Snowman]

Yes, I'm using a 44pin Xllinx 9572 CPLD - common chip...and I realise that it should automaticall be recognoised and added as an icon to the screen but it doesn't...I don't know why...I've dbl checked the circuit wiring, it looks ok, I've shortened all the lead such that the entire set of connections from parallel port to cpld is less than 40cms...not sure what else to do...what other things should I check for???

Thx,
Avital

 

[kinjalgp]

Is 0x378 the address your LPT2 port? Because most of the parallel ports that I've worked on have 0x378 for LPT1. Check this out.

 

[Snowman]

Yes, I've considered this...I changed it back to lpt1, made sure that my bios is set to "bi-directional" and that pnp emulation is setup. Basically, I did everything I could find on the Xilinx site. This is very odd, because I've seen this schematic (modified slightly even, in some) in 3 diff. places. It's still on the Xilinx website and is explained fairly well...not sure what else to do. Have you actually made this simple circuit and managed to get it to work???

 

[kinjalgp]

No I haven't made it but I am aware of problems with parallel ports. I have 3 parallel port based device programmers lying in my junk. They all had some or the other problem. . Changing the Parallel port modes use to affect their working even though non of them used bi-directional feature.

Check this schematic with that of yours.
https://www.xilinx.com/support/programr/files/0380507.pdf

 

[Snowman]

Yup, that's the one I'm using as my main source - I just checked others to make sure. I think it may be noise problems on the JTAG lines...even though there are caps on those lines - considering a schmitt trigger. Any other ideas on the problem may be? Any pointers on parallel port interfacing musts?

 

[kinjalgp]

Try changing your LPT1 mode to "Normal", ECP, EPP or ECP+EPP in BIOS and check your software for each different mode. If you still can't get it, then I think your CPLD is faulty and not responding to ID request. Replace it.

 

[Snowman]

I've already tried all of those, and I've consulted the Xilinx website about that too - I really don't think it's the lpt port itself. From what little I could gather on newsgroups, there may be a problem with the circuit in general as the HC125's are extremely sensitive to noise. I'm considering 7414s and/or caps on the inputs to the 125s. But, before I start soldering stuff again I was wondering if anyone could suggest some ideas on this issue of noise.

Thx,
Avital

 

[kinjalgp]

Well, in order to minimize noise in your system following care should be taken
1) Your power supply should be as pure and stable as possible. Use in-line choke filters (ferrite bead) for reducing noise ripples in Vcc line.
2) Always use decoupling capacitors across the power pins of all ICs in your system. 0.1uF is suitable value. This reduces noise considerably.
3) Do not take TTL signals to very long distance. Keep distance between your PC and circuit to a minimum.

I doubt whether you have connected decoupling capacitors in your circuit because they are not shown in the schematic. If not try that first. May be it will solve the noise problem.

 

[Snowman]

Actually,

I fixed the initial problem. The software now does basic functions like recognise the chip, calcs the checksum, even erases the chip. However, I am not able to program anything - how long would such a process take anyway? I fixed the problem by adding a 1k pullup resistor to TDO. Was wondering if anyone had opnions on what was going on and/or has experience with JTAG and can explain this to me.

Thx
Avital

 

[laroche73]

JTAG programming cable

Hi, Snowman. The first thing I'd suggest is to check your signal levels with a scope, if you haven't done so already. Noise could be the problem, but rule out the simple things first. There's no substitute for hooking up a scope and viewing the actual signals.

As shown in the schematic, the cable buffer chip draws power from your prototype system. What are you using for the cable VCC, 3.3V or 5V? (The XL inputs are 5V tolerant). The cable schematic shows a schottky diode in series with your VCC supply -- did you use a schottky type or a standard silicon diode like the 1N914? (schottkys have a lower forward voltage drop)

A few more questions,

1) Are you driving the cable from a desktop or laptop parallel port? Again, check the levels.

2) The schematic shows a 5.1K resistor to VCC on TDO. Having to add another 1K pullup to get things "partially" working is a suspicious sign. The signal levels may be just making it, and that would explain being able to do short operations like getting the device ID, but failing longer operations like programming the device. Noisy lines can also cause this problem. Perhaps one bit out of 100K fails. When short operations work and long ones don't, it should raise a red flag (and make you pull out the scope :wink: ).

Also, a more detailed description of your prototype board setup might help (power supplies, decoupling caps & location, etc.)

I have a Xilinx PP cable that essentially matches the posted schematic (I popped the cover years ago and looked it over). It's about 3 ft long and works fine with the Virtex board I have from Avnet (two JTAG devices, 18V01 and a XC2V40).

- Claude

one more thing. I found a Xilinx databook that covers the XC9500XL chips, and it mentions that the inputs have a small amount of hysteresis, around 50mV.

 

[Snowman]

Claude,

Unfortunately, I can't access to a scope very easily - I had one for about a week or so but it's gone now. I'm using 5V as VCC, 1N4148
Schottky diodes, and a standard PC desktop parallel port. The circuit is already soldered onto a veroboard as I thought it would work "out of the box", I'm feeding the circuit 5V from a 7805 (100mA version) along with 10nF and 47uF caps as noise filters. The input to this power supply is also a regulated 5V signal from another 7805 with some caps as my main power supply is 13V, and that exceeds that max input for the 78L05. All the leads/wires have been kept extremely short - the wires from the parallel port to the circuit is ~20cms, and the wires from the programmer to the socket board is about 5cms.

I totally agree that I need a scope but it doesn't seem likely I'll be getting access to one anytime soon. Noise and waveform problems seem to be the underlying cause from what I've gathered from the Xilinx answer site. In fact, the 100pF caps are one attempt by Xilinx the corner freq - filtering it to 100MHz. But the slope gets extremely slow, and with added noise, is much higher than 50mV so using 50mV schmitt triggers such as 7414s would not work. So, instead, I tried soldering a 1K resistor between the output/input of one of the 74125 gates, in fact, for CLK, DIN, and PROG. I've also tried a weak (1k) pullup on PROG and CTRL. None of this has worked. Perhaps using LS components with a lower switching voltage may work (I have yet to test this). I suppose there are no "canned" solutions for this type of thing.... It's strange that pretty much all works except programming.

What do you think?
Thanks,
Avital

 

[Snowman]

Claude,

Two other things I noticed/should mention:
1) IDCODE looping works flawlessly for any # I pick - I've even tried a number as high as 50,000

2) If I select the program option, it erases successfully, then prints that it is programming - an operation which never ends and forces me to kill the process. However, when I do a "blank check" on the cpld, it performs the operation successfully telling me that the part is not blank. Which got me thinking - maybe it programs the cpld correctly but, due to problems with the software or voltage levels, it never ends the operation properly from the software's point of view but the operation is, in fact, complete.

What do you think?
Avital

 

[laroche73]

JTAG programming cable using PP

Avital, trying to diagnose the problem without a scope is a bit like flying blind. It would help you rule out your hardware as the problem. Without actually observing the signals, the best you can do is guess and try some likely fixes, as you've been doing. The signal edge rates on a parallel port are not all that fast (relatively speaking), and the problem may or may not be "noise". Although it's a good idea to keep your cables as short as possible, keep in mind the PP cable I have from Xilinx uses a similar circuit (without any mods) and is just under 6 ft. long. It programs the JTAG parts on the two FPGA boards I have without errors. I think the data rate is somewhere in the neighborhood of 100 kbps.

Let's clarify a few things about your setup, I'm still suspicious about your signal levels:

1) The 1N4148 is not a schottky diode, its equivalent to a 1N914, and the forward voltage drop can be as high as 0.75 - 1V, depending on the load current (which won't be very much for two 74HC125s). A schottky type like the recommended 1N5817 should have a forward voltage drop of around 0.3V at low load currents. None of this should matter much if the diode is being fed off a 5V supply.

https://www.electro-tech-online.com/custompdfs/2003/12/1N4148.pdf
https://www.electro-tech-online.com/custompdfs/2003/12/1N5817-DPDF.pdf

2)

The input to this power supply is also a regulated 5V signal from another 7805 with some caps as my main power supply is 13V, and that exceeds that max input for the 78L05.

I may have misunderstood this - are you feeding a 78L05 (the cable's power source) with the output from another 7805? This would not be a good idea, as the '78 regulators need a few volts of overhead on the input side. What does the voltage measure at pin 14 on the 74HC125s?

3) Are you using an 'XL part and a 3.3V regulator to power it?

4) Noting your last post, I agree that the whole trouble could be with the programming software, just try to rule out any hardware problems first. To check whether the part is actually getting programmed, try a very simple test. Program the part to have a single inverter, using one input and one output pin. Or some other circuit that's easy to check after a programming attempt.

Good luck, and try to borrow a storage scope from someone!

 

[Snowman]

Claude,

Definitely flying blind as far as seeing the signals but it'll be a while before I get access to a scope - I'll try to get access to the uni labs. I have been suspcious about my construction because-after browsing google groups-I noticed that a lot of people said that their Xilinx-bought cables worked fine on most computers (without modification of circuit).


1) I used the 1N4148s b/c some book I used at the store said it was equiv to the suggested diode. Do you think I should make an effort to find the diodes and replace them?

2) You understood perfectly. I'm sorry I wasn't too clear, upon rereading my post I noticed a few words missing, I should proof read before posting But, anyway, that's gone now...I'm using a cheap transformer that's feeding the 78L05 directly now. I measured the VCC for the 74HC125, it's 5V

3) I don't know if I mentioned this before, but I am testing using XC9572-15PC44C, my layout is:

44pin-PLCC socket--wires-->programmer--wires-->parallel port

The wires are extremely short as I mentioned before, I'm using a seperate board for the PLCC socket because I've wired every pin in order to a pin of a normal machined IC socket that's also on the same board. That way I can easily access all the CPLD pins for testing after programming. Please let me know if I haven't explained this clearly enough. I'm feeding the CPLD 5V directly from the "clean" 78L05.

4) Exactly, I was just wondering if you had direct experience software bugs in the WebISE tool. I should test it with an inverter, so far I've been using a 10input AND gate...I'll post as soon as I do this...

Thanks for the great advice, as usual
Avital

 

[laroche73]

diodes

Glad to help, or at least offer some advice . Yes, I've run into some issues with the WebISE software, but they had more to do with downloading the correct core packages from the Xilinx website (I think I had to download and install the Spartan core modules in order to get code targeted for the Virtex parts to compile. It's been a while since I've used the software).

1) I used the 1N4148s b/c some book I used at the store said it was equiv to the suggested diode. Do you think I should make an effort to find the diodes and replace them?

No, though it may have made a difference if you were trying to run the cable off a 3.3V supply. Often schottky diodes are used in circuits like this or in battery backup circuits because of their low forward voltage drop. The 1N4148/914 is not equivalent in that respect.

 

[Snowman]

Claude,

Success!!! Shortly after I had posted last I simply restarted the iMPACT software. After this, the programming and verification session went by just fine. I have tested the functionality with a 10-input AND gate and with an inverter - both worked fine. In addition to the normal circuit I have rudimentry schmitt triggers based on wiring a resistor between input/output on several 74HC125 gates, pull up resistors on all 4 JTAG lines and now a direct input from a "raw" power supply. I suspect that the two major factors here are the direct power supply feed and a pull up on TDO - I could probably do without the others, but I'm not willing to screw around with the circuit at this point

I will now be focusing my efforts on the VHDL and logic for the circuit discussed in another post - the one with many sensors, as I'm sure you remember. Will keep posting questions...

Thanks again for your help - always appreciated!
Avital