problem with 40192 timer

[fezder]

Hi,
i apologice if there is this cind thread/problem, but i have the followind problem which has been for sometime now:

i try to make knight rider circuit which has leds that run one direction and comes back again. i have 10 leds so sequence would be: 0....9->9....0
im using 40192 4 bit counter, ne555 timer and 4051 de/multiplexer

i have followind ic:s which i can currently use at design:
NOR, NAND, AND, XOR, XNOR, D-FLIP DLOP , inverter and scmitt trigger
also 4017 counter

tell/ask if you have anything on your mind

 

[ericgibbs]

Hi,
i apologice if there is this cind thread/problem, but i have the followind problem which has been for sometime now:

i try to make knight rider circuit which has leds that run one direction and comes back again. i have 10 leds so sequence would be: 0....9->9....0
im using 40192 4 bit counter, ne555 timer and 4051 de/multiplexer

i have followind ic:s which i can currently use at design:
NOR, NAND, AND, XOR, XNOR, D-FLIP DLOP , inverter and scmitt trigger
also 4017 counter

tell/ask if you have anything on your mind

hi and welcome.
What is the problem you are having with your design, what is not working correctly.??

 

[fezder]

oh, sorry how stupid i was.....totally forgot to add the problem:

my circuit seems to be stuck in changing counting direction, when it reacses one end, it goes only one step back-forth motion only: 0....9->9,8,9,8,9....

do you need my scematic im using?

 

[ericgibbs]

oh, sorry how stupid i was.....totally forgot to add the problem:

my circuit seems to be stuck in changing counting direction, when it reacses one end, it goes only one step back-forth motion only: 0....9->9,8,9,8,9....

do you need my scematic im using?

hi,
If you could post your schematic it would be helpful.

 

[fezder]

View attachment 63323View attachment 63324

here are two schematics which i used. they both have same problem. theyre from local forum, where i also asked for help

 

[ericgibbs]

Ok,
I will look over your circuit.

 

[ericgibbs]

hi,
One problem is that the unused clock has to be High in order to enable clocking one the other clock input, look at this image.

With the NORs gate connected to the clocks this cannot happen.

 

[fezder]

Hmm, yes i read that at the datasheet, but why i didnt realice that
count up: count down=1 count up=PULSE
count down: count down=PULSE count up=1

but shouldnt that d-flip flop keep either up/down to solid 1 state and after cycle change state?
*edit: d-flip flop keeps only one input of NOR gate solid 1/0, other is affected by clock pulse right?
if i read NOR truth table correctly, i should use AND gate instead of NOR, as it seems to be opposite of NOR?
NOR
A | B | Y
0 | 0 | 1
1 | 0 | 0
0 | 1 | 0
1 | 1 | 0

AND
A | B | Y
0 | 0 | 0
1 | 0 | 0
0 | 1 | 0
1 | 1 | 1

 

[ericgibbs]

but shouldnt that d-flip flop keep either up/down to solid 1 state and after cycle change state?

The D F/F will do that OK, but its the action of the NOR's connected to the F/F outputs which is the problem.
The output of one of the NOR's is always going to be 0. [low], which blocks the 193 Clock.

I will look at your AND gate idea.

 

[ericgibbs]

*edit: d-flip flop keeps only one input of NOR gate solid 1/0, other is affected by clock pulse right?
if i read NOR truth table correctly, i should use AND gate instead of NOR, as it seems to be opposite of NOR?

hi,
This is your circuit in simulation, you should be able to see what is wrong with the logic.

I used a 193, dont have a 192 model, but the results are the same.
E.

 

[fezder]

well i must say, i dont quite understand this picture, at least all of it.
i think i understand to read right colour paragraphs: the reading order is from left to right, at top where it reads different voltage monitor names. And the colour code is also specific-given for certain voltage monitor, as v (cdn_) is purple?

but what i should look at this picture? it seems odd thought, at least at those v (cup_) and v(cdn_) but dont know why

 

[ericgibbs]

well i must say, i dont quite understand this picture, at least all of it.
i think i understand to read right colour paragraphs: the reading order is from left to right, at top where it reads different voltage monitor names. And the colour code is also specific-given for certain voltage monitor, as v (cdn_) is purple?

but what i should look at this picture? it seems odd thought, at least at those v (cup_) and v(cdn_) but dont know why

hi,
By looking at the PLOT of the logic states of the F/F and the other Gates you should be able to determine which logic function is causing the circuit to malfunction.

I would suggest you reduce the circuit to only an UP counter, get that working OK and then change it to a DOWN counter which works.

This will give you and understanding of what action is required at the FF and the clock input gates.

If you get stuck I will be pleased to post a working circuit, but I thought you may prefer to solve the problem yourself.

 

[fezder]

Ok, i will try this. this is actually the way i prefer to solving problems, by myself as it teaches somewhat more than reading answer rightaway.....ill keep you posted of my progress, thanks for your patience so far

 

[fezder]

hi,
i got it now working as up counter only, and down counter only, but i have no idea how to make it switch direction, can you give a clue?

 

[ericgibbs]

hi,
i got it now working as up counter only, and down counter only, but i have no idea how to make it switch direction, can you give a clue?

hi,
OK.
As you know the unused clock input of the 192 must be high [1] in order to Enable the other clock input to clock the counter.

The problem is the terminal count, consider the /TCup output pin.

When the counter reaches its maximum count due to the last high going edge of the clock pulse, the /TCup is still high [1].
The /TCup only goes low when the input clock goes low[0].

You are using the /TCup low going edge to trigger the F/F, this means the F/F changes over and the up clock pin goes high, which has to do in order to enable the down count clock input.

The 192 'sees' this unwanted low to high transition on its Up clock and so it counts back to zero.... this zero output now sets the /TCdwn low.... and so on.

I hope you follow that OK.

Look the datasheet extract about the /TC

 

[fezder]

so my circuit is jammed because it tries to change direction all the time when it reaches either end? should i make some cind of dealy for this circuit, that it needs two pulses to change direction? i read somewhere about this cind of delay using logic gates, cant remeber wich one thought :S

 

[fezder]

now i tried even using outputs q0 and q0 (9) which i tied to XOR gates to make switching pulse, but of course it comes all the time again 0....9->9....9.....9
am i making any progress, or is this all terribly wrong?

 

[ericgibbs]

now i tried even using outputs q0 and q0 (9) which i tied to XOR gates to make switching pulse, but of course it comes all the time again 0....9->9....9.....9
am i making any progress, or is this all terribly wrong?

As you are using the 192 to drive a 4051 demux [ 8 outputs] why not consider decoding the 8th count of the 192 to clock the F/F.

The 192 /TC outputs are designed to drive the next 192's clocks in a series counter chain.

EDIT:
This is one option.

 

[fezder]

Hi,
Thank you very much of your help, it now works as desired, good to know there are people willing to help a beginner of electronics
what do you think, was i far off finding the qorking circuit?

 

[ericgibbs]

Hi,
Thank you very much of your help, it now works as desired, good to know there are people willing to help a beginner of electronics
what do you think, was i far off finding the qorking circuit?

hi,
I think you were very close to fixing it.

The 192 can be difficult to use in circuits like yours, the /TC cause many problems.