Power Supply Rejection in LTSpice

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AsiongMartinez12

New Member

• Feb 7, 2016

• #1

Hi. I am struggling in getting the power supply rejection in LTSpice. I am to design an LDO of regulated output of 0.8 with accuracy of +/- 2%. The power supply rejection is the only thing left. please help me get a 20dB PSR

 

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alec_t

Well-Known Member

Most Helpful Member

• Feb 7, 2016

• #2

The default MOSFETS aren't much use. Specify the actual MOSFET models and see what happens. Can you post your asc file?

 

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AsiongMartinez12

New Member

• Feb 7, 2016

• #3

of course... here is the file alec_t could you help me out here

 

alec_t

Well-Known Member

Most Helpful Member

• Feb 7, 2016

• #4

Sorry, I've no experience of playing about with the FET parameters (I just pick a FET from a library). Perhaps someone else can help there.

 

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AsiongMartinez12

New Member

• Feb 7, 2016

• #5

Oh ok alec_t could you please suggest someone you know here that could help I really need this.. Thank you

 

alec_t

Well-Known Member

Most Helpful Member

• Feb 7, 2016

• #6

EricGibbs and MikeMl, to name but two, are members with a lot more LTspice experience than me.

 

crutschow

Well-Known Member

Most Helpful Member

• Feb 7, 2016

• #7

The power supply rejection is simply the output AC voltage versus input AC voltage (ripple).
Set the AC value to 1V in the input DC source, with an output resistive load sufficient to properly bias the circuit (the circuit you posted does not seem to tolerate any load).
Then do an a AC analysis, which will show how much the input voltage is attenuated at the output versus frequency (shown in dB).

 

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AsiongMartinez12

New Member

• Feb 7, 2016

• #8

Thank you alec_t

 

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AsiongMartinez12

New Member

• Feb 7, 2016

• #9

Hello crutschow what do you mean I dont have a load in my circuit.. Could you help me out on that part..

 

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AsiongMartinez12

New Member

• Feb 10, 2016

• #10

ericgibbs could you help me out on my problem

 

crutschow

Well-Known Member

Most Helpful Member

• Feb 12, 2016

• #11

AsiongMartinez12 said:

Hello crutschow what do you mean I dont have a load in my circuit.. Could you help me out on that part..

Click to expand...

True, you don't have a load on the amp.
And my simulation showed that it can't tolerate any load, which would seem to make the circuit rather useless.

 

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AsiongMartinez12

New Member

• Feb 12, 2016

• #12

crutschow said:

True, you don't have a load on the amp.
And my simulation showed that it can't tolerate any load, which would seem to make the circuit rather useless.

Click to expand...

oh ok could you please show me how it should be done... I just need a start to be able to continue.. please crutschow

 

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AsiongMartinez12

New Member

• Feb 12, 2016

• #13

alec_t could you help me design an LDO?

 

alec_t

Well-Known Member

Most Helpful Member

• Feb 12, 2016

• #14

Thanks, Asiong, for your belief that I could but as I said, I have no experience with using/choosing FET parameters (at the CMOS process level). I can't design the FETs themselves.
If you want a design using existing specific FET models included in the component library that comes with LTspice, then googling "low dropout regulator schematic" gives you many options to study and perhaps use as a basis.
It would help to know what course work your design brief is meant to be based on.

 

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AsiongMartinez12

New Member

• Feb 12, 2016

• #15

oh all right thank you alec_t