I've used DDS in the past also. Use to be quite expensive chips but now at least for some, they can be quite cost effective. They do require a post low pass filter but that's not to hard to do. DDS clock input must be X2+ higher then the highest desired output frequency. Some jitter and spurs are produced but still useful for all but the most demanding spectral purity applications.
I've read that one current state of the art solution for the demanding application of a very low noise and clean local oscillator for communication receivers is having a DDS drive a PLL. The DDS gives precise frequency control and the PLL (via a VCO) cleans up the spurs.
I would think that a DDS would have lots of jitter unless you clock it relatively fast. A DDS with a 20Mhz clock trying to generate 131,072kHz would produce quite a bit of jitter. Choosing a crystal frequency which evenly divides down, will produce the best results.
Bill, I finally (my power supply died, had to fix it) breadboarded the whole danged *25 multiplier using a 74HCT4046 and a couple of HCT161's (and an HCT04). It seems to work really well. If you're still interested, I'll post the schematic.
You're welcome. Did you test it already?
I'll be so happy when the elections are over. I'm sick of the negative campaign ads, half-truths, and my candidate's opponent. I'm not gonna mention his name, because this is not the forum for political discussions.
OK, here are the changes for 3.2kHz in / 80kHz out. I think I made mistakes calculating the loop filter in the previous design, although it seemed stable.
I tested the new version by perturbing the loop at about 1Hz and watching the error voltage settle.
Thanks Roff
I can't say the TI 4046 datasheet is among the most readable I've ever read.
I do recall but can no longer find an old Quick BASIC program that helped with the loop & filter calculations.
Thanks Roff
I can't say the TI 4046 datasheet is among the most readable I've ever read.
I do recall but can no longer find an old Quick BASIC program that helped with the loop & filter calculations.
Just an update, I found the hopefully (yet untested by me) little PLL IC for the clock. A ICS501 PLL clock multiplier.
This wee 8pin SOIC has 9 preset multipliers and requires no external components.