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PLL question, will a 4046 clocked at 512Hz be able to reliably generate 131,072Hz ?

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I've used DDS in the past also. Use to be quite expensive chips but now at least for some, they can be quite cost effective. They do require a post low pass filter but that's not to hard to do. DDS clock input must be X2+ higher then the highest desired output frequency. Some jitter and spurs are produced but still useful for all but the most demanding spectral purity applications.

I've read that one current state of the art solution for the demanding application of a very low noise and clean local oscillator for communication receivers is having a DDS drive a PLL. The DDS gives precise frequency control and the PLL (via a VCO) cleans up the spurs.

Lefty
 
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How about something like one of these ?
**broken link removed**
 
I would think that a DDS would have lots of jitter unless you clock it relatively fast. A DDS with a 20Mhz clock trying to generate 131,072kHz would produce quite a bit of jitter. Choosing a crystal frequency which evenly divides down, will produce the best results.
 
Next question...

4046 with a /25 using a pair of 74HC160 programmable synchronous dividers.

FIN = 1.6kHz
FOUT = 40kHz

What would the loop filter be? the FIN will never vary. Can I use asynchronous dividers like the 74HC90?
 
Next question...

4046 with a /25 using a pair of 74HC160 programmable synchronous dividers.

FIN = 1.6kHz
FOUT = 40kHz

What would the loop filter be? the FIN will never vary. Can I use asynchronous dividers like the 74HC90?
Bill, I finally (my power supply died, had to fix it) breadboarded the whole danged *25 multiplier using a 74HCT4046 and a couple of HCT161's (and an HCT04). It seems to work really well. If you're still interested, I'll post the schematic.
 

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It's perfect, thank you Roff. Hey I'm only 30 posts ahead of you!

Enjoy your elections Tuesday.
You're welcome. Did you test it already?
I'll be so happy when the elections are over. I'm sick of the negative campaign ads, half-truths, and my candidate's opponent. I'm not gonna mention his name, because this is not the forum for political discussions.
 
OK, here are the changes for 3.2kHz in / 80kHz out. I think I made mistakes calculating the loop filter in the previous design, although it seemed stable.
I tested the new version by perturbing the loop at about 1Hz and watching the error voltage settle.
 

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Thanks Roff
I can't say the TI 4046 datasheet is among the most readable I've ever read.
I do recall but can no longer find an old Quick BASIC program that helped with the loop & filter calculations.
 
The Philips 74HC4046 datasheet is the best.
The spec's are a little different among the manufacturers.
 
Thanks Roff
I can't say the TI 4046 datasheet is among the most readable I've ever read.
I do recall but can no longer find an old Quick BASIC program that helped with the loop & filter calculations.
I'm using Phaselock Techniques (1966) by Floyd M. Gardner. I hope physics hasn't changed in 42 years.:D
 
Just an update, I found the hopefully (yet untested by me) little PLL IC for the clock. A ICS501 PLL clock multiplier.
This wee 8pin SOIC has 9 preset multipliers and requires no external components.
 
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