PLL in DSPIC

[Angy]

Can someone please explain the function of PLL in the oscillator config in Dspic?
PLLFBD?

 

[Nigel Goodwin]

Never having looked at one, I would presume it's so you can use a faster clock while using a slower crystal.

The 18F series do this, a 40MHz crystal would be difficult to make, and very expensive - so it uses a 10MHz crystal (easy to obtain and cheap) and a x4 PLL.

 

[Angy]

Thanks nigel

 

[nickelflippr]

In the case of the PIC32, there are a ton of clock registers, including a core and peripheral bus clock. Beside the PLL, there are multipliers AND divisors to concoct any sort of clock you may desire. Best to grab the particular data sheet to see what's up. Guessing the PLLFBD is some sort of divisor.

 

[felis]

PLLFBD?

It's PLL feedback divisor. It provides a factor, by which the input to the VCO is multiplied. This factor must be selected such that the resulting VCO output
frequency is in the range of 100 MHz to 200 MHz ( for dsPIC33F).

 

[blueroomelectronics]

I've used that very handy PLL in a 24H project recently.