Pipelined Datapath for computer architecture

[siyom]

So I'm doing pipelined datapaths and i'm finding it very hard to understand.I'm familiar with single and multiple clock cycle datapaths but pipelined is proving to be a problem.
I've attached a picture of the datapath,I dont understand how they got the values 104 and 108 in the ID/EX stage.Also the 105 in the EX/MEM stage as well as the 210 in the MEM/WB stage.

All registers initially have 100 stored in them.Anyone care to explain this?the whole forwading thing is pretty confusing as well,

 

[kubeek]

Not sure about the numbers, they seem rather weird and seem to denote the registers rather than values in the registers..
But the whole point of forwardin is this: The ADD $3,$4,$8 presumably wants to store the result into $3. The instruction behind it, the ADD $2,$2,$3 wants to use the reult of that operation, but without forwarding it would have to wait two cycles for the result of the first add to get written into the register during the writeback stage.
With forwarding, you can put this result straight into the ALU, thus eleminating the pipeline stall.

 

[siyom]

So basically you read this datapath from the right and work your way backwards till you reach the instruction fetch?cause that's the only way that makes sense to me.if $5+$5=210 stored in $8
$8-$5=105 stored in $2
etc....