PIC32MZ Errata

[Gobbledok]

This is a bit of a rant thread I suppose. I was having a look at what's around when it comes to microcontrollers (as I do) and was attracted to the PIC32MZ due to it's high speed (200MHz) and loads of internal RAM (512kB).

I thought I'd have a look at the errata to see what was in there and to my surprise it was a pretty full document.

The main ones which would concern me:

8. Module: I/O Port
The Open Drain selection (ODCx) on I/O port pins
is not available when the pin is configured for
anything other than a standard port output. the
Open Drain feature is not available for dedicated
or remappable Peripheral Pin Select (PPS) output
features.
Work around
None.

If you cannot use open-drain outputs for anything other than a normal IO port then you cannot use external pullups to 5v when using the (for example) SPI. You can only interface with other 3.3v devices unless you bit-bang.

10. Module: Oscillator
The Ceramic Resonator cannot be used as an
input to the Oscillator module (OSC1/OSC2 pins).
Work around
Instead, use either a crystal oscillator or the
external clock.

Cannot use a ceramic resonator as the main oscillator.

11. Module: Secondary Oscillator
A crystal oscillator cannot be used as the input to
the Secondary Oscillator (SOSCI/SOSCO pins).
Work around
Instead, use the external clock.

Can only use an external clock for the 32.768KHz RTC input.

18. Module: USB
The USB module will not function if the device
enters Sleep mode and the USB PHY is turned off
by setting the USBSSEN bit in the CFGCON
register to ‘1’.
Work around
Keep the USB PHY operational in Sleep mode by
setting the USBSSEN bit to ‘0’.

If using the USB, you cannot disable the USB PHY and enter sleep mode at the same time.

19. Module: USB
The USB module requires a start-up delay.
Work around
When enabling the USB PLL, add a three second
delay before turning on the USB module.

3 Seconds!

22. Module: Watchdog Timer
When the Watchdog Timer is used in Window
mode, the module may issue a Reset even if the
user tries to clear the module within the allowed
window.
Work around
None.

You cannot use the Watchdog Timer in Window mode.

23. Module: Watchdog Timer
When the Watchdog Timer expires during Sleep
mode, it causes a Reset rather than a Nonmaskable
Interrupt (NMI).
Work around
None.

Will reset instead of interrupt.

24. Module: PMP
PMP address lines block the use of lower-order
functions when the PMP is used but the
corresponding bit in the PMAEN register is
cleared.
Work around
Higher-order functions are available and should be
used instead. As described in the previous
example, EBIA5 and AN34 would be available.

So if I were to use the Parallel Port for an LCD, I cannot use any of the unused address pins (basically all of them) as an I/O port?

25. Module: I2C
Setting the PEN bit to send a Stop does not
release the SDA line.
Work around
The I2C module must be turned ON before every
transaction, and turned OFF after the transaction
completes.

You must enable and disable the I2C port for each and every transaction.

27. Module: Random Number Generator
True RNG mode does not function.
Work around
Instead, use Pseudo-Random Number Generator
(PRNG) mode.

The RNG does not work.

34. Module: SQI
Clock speed for read operations does not meet the
maximum specification (SQ10) of 50 MHz. For
read operations the maximum clock is 25 MHz.
Work around
None.

37. Module: Comparator
The Input Offset Voltage parameter (D300) is not
within the published data sheet specification. The
typical value is ±30 mV.
Work around
None.

The datasheet says ±10 mV.

38. Module: I/O Pins
When the Secondary Oscillator is disabled
through the FSOSCEN bit (DEVCFG1<6>), the
SOSCO pin does not tri-state and is driven to Vss.
An I/O pin shared with the SOSCO function cannot
be used as a general purpose input or output.
Work around
None.

So I cannot use a crystal as the secondary oscillator, and I cannot use the (now unused) SOSCO pin as a general Purpose IO?

42. Module: 5V Tolerant I/O Pins
When internal pull-ups are enabled on 5V tolerant
pins, the level as measured on the pin and
available to external device inputs may not exceed
the minimum value of VIH, and therefore qualify as
a logic “high”. However, with respect to the PIC32
device, as long as VDD ≥ 3V and the load doesn't
exceed -50 μA, the internal pull-ups are
guaranteed to be recognized as a logic “high”
internally to the device.
Work around
It is recommend to only use external pull-ups:
• To guarantee a logic “high” for external logic
input circuits outside of the PIC32 device
• For PIC32 device inputs, if the external load
exceeds -50 μA or VDD < 3V

There are internal pullups on 5v tolerant IO pins but it is recommended not to use them.

43. Module: ADC
The ADC module has the following restrictions:
1. SH0 through SH4 functionality is not supported.
Sampling must be performed on SH5
only.
2. Automatic Channel Scan mode is not supported.
Channel Scan must be performed
manually in software.
Work around
None.

Only 1 out of 5 sample and holds works.

46. Module: Oscillator
Switching the System Clock (SYSCLK) to the
System PLL (SPLL) causes a device Reset. This
affects both software and hardware (IESO) clock
switching.
Work around
To switch the clock source, disable IESO, and
execute the following steps in software:
1. Reduce the speed of all peripheral buses to
128:1 through PBCLKx (where ‘x’ ≠ 7) and
reduce the speed of the CPU bus to 128:1
through PBCLK7.
2. Perform the clock switch.
3. Set the speed of the CPU bus to the
previous clock switch divisor and set the
speed of the peripheral buses to their
previous clock switch divisor.

To switch to the PLL you need to lower the speed of all of the peripheral busses before switching and then raise the speed once done or it will reset.

49. Module: Deadman Timer
The Deadman Timer should trigger a Non-
Maskable Interrupt (NMI) when the timer runs out
or when an incorrect value is written to the
DMTPRECLR or DMTCLR registers. Instead, the
Deadman Timer triggers a device Reset without a
NMI.
Work around
None.

Will reset instead of interrupting.


I don't mean to hate on microchip because I learnt using PIC's but some of these are some pretty serious problems and makes me think that it wasn't even ready for release yet.

Does anybody know how the errata process works? As in are these problems found before releasing it to the public or are these problems found via feedback from users? Do they even test their design before selling them?

I bet they aren't selling many of these and needless to say I stopped looking at them after looking at the errata.

 

[NorthGuy]

And there are hundrends more which Microchip haven't found yet. The 32MZ series is very new, so it's nothing unusual. I'm sure it'll be better in few years from now. Meanwhile, use 16F instead

 

[Gobbledok]

Haha there's a bit of a difference between a 16f and a 32MZ but I see your point. The 16f is a lot more mature.

TBH I can't say that I have looked at a products errata at the start of the lifecycle so I had no idea if this is common or not.

I just thought that there would be a better process I guess. For example how hard would it be to test the primary and secondary oscillators with a crystal before production? (the primary oscillator only works with a crystal with the latest silicon revision and the secondary oscillator doesn't support a crystal at all).

A quick glance at the PIC32MX errata shows that there is still almost 50 silicon issues still with that chip. That was released in 2008 (I think). What is considered a mature product?

The LPC176x (released 2009 I think) errata shows only 14 issues.

The STM32 (released 2011 I think) errata shows no silicon issues, only an update to a legal notice.

Once again I don't mean to hate on microchip but is there something I'm missing?

 

[nsaspook]

A quick gland at the STM32 errata shows no silicon issues, only an update to a legal notice.

Once again I don't mean to hate on microchip but is there something I'm missing?

The MZ still really in a pre-production state IMO. True A versions will be available maybe in March 2015.
**broken link removed**
https://www.st.com/st-web-ui/static...echnical/document/errata_sheet/DM00037591.pdf

For complex chips this is fairly normal, nothing on either is/was a complete show-stopper for most people developing new products.

 

[Gobbledok]

Sorry nsaspook I did make a couple of changes to that post after you quoted it.

That would explain it but I see no mention of anything to that effect on the PIC32MZ product page.

I guess I am a bit surprised and have not some across this before, not to say it is not common.