Makaram
Member
Hi all,
I've been running with the pic32's for a few months now with some great successes but there's one thing that's always baffled me..
My peripheral clk doesn't seem at all affected by the Peripheral Clock Divisor. Pb_clk is always = to sys_clk.
To prove this is the case I used UART BRG of 519 to achieve 9600 baud and it worked. This is the calculated value based off of a 80000000 clk not the configured sysclk/4 pbclk.
Whether this is a bug or a oversight on my part I do not know, perhaps someone could help me.
I've been running with the pic32's for a few months now with some great successes but there's one thing that's always baffled me..
My peripheral clk doesn't seem at all affected by the Peripheral Clock Divisor. Pb_clk is always = to sys_clk.
To prove this is the case I used UART BRG of 519 to achieve 9600 baud and it worked. This is the calculated value based off of a 80000000 clk not the configured sysclk/4 pbclk.
Whether this is a bug or a oversight on my part I do not know, perhaps someone could help me.
Code:
// PIC32MX564F128H Configuration Bit Settings
// DEVCFG3
// USERID = No Setting
#pragma config FSRSSEL = PRIORITY_7 // SRS Select (SRS Priority 7)
#pragma config FCANIO = ON // CAN I/O Pin Select (Default CAN I/O)
#pragma config FUSBIDIO = ON // USB USID Selection (Controlled by the USB Module)
#pragma config FVBUSONIO = ON // USB VBUS ON Selection (Controlled by USB Module)
// DEVCFG2
#pragma config FPLLIDIV = DIV_3 // PLL Input Divider (3x Divider)
#pragma config FPLLMUL = MUL_20 // PLL Multiplier (20x Multiplier)
#pragma config UPLLIDIV = DIV_3 // USB PLL Input Divider (3x Divider)
#pragma config UPLLEN = ON // USB PLL Enable (Enabled)
#pragma config FPLLODIV = DIV_1 // System PLL Output Clock Divider (PLL Divide by 1)
// DEVCFG1
#pragma config FNOSC = PRIPLL // Oscillator Selection Bits (Primary Osc w/PLL (XT+,HS+,EC+PLL))
#pragma config FSOSCEN = OFF // Secondary Oscillator Enable (Disabled)
#pragma config IESO = OFF // Internal/External Switch Over (Disabled)
#pragma config POSCMOD = HS // Primary Oscillator Configuration (HS osc mode)
#pragma config OSCIOFNC = OFF // CLKO Output Signal Active on the OSCO Pin (Disabled)
#pragma config FPBDIV = DIV_4 // Peripheral Clock Divisor (Pb_Clk is Sys_Clk/4)
#pragma config FCKSM = CSDCMD // Clock Switching and Monitor Selection (Clock Switch Disable, FSCM Disabled)
#pragma config WDTPS = PS1048576 // Watchdog Timer Postscaler (1:1048576)
#pragma config FWDTEN = OFF // Watchdog Timer Enable (WDT Disabled (SWDTEN Bit Controls))
// DEVCFG0
#pragma config DEBUG = OFF // Background Debugger Enable (Debugger is disabled)
#pragma config ICESEL = ICS_PGx1 // ICE/ICD Comm Channel Select (ICE EMUC1/EMUD1 pins shared with PGC1/PGD1)
#pragma config PWP = OFF // Program Flash Write Protect (Disable)
#pragma config BWP = OFF // Boot Flash Write Protect bit (Protection Disabled)
#pragma config CP = OFF // Code Protect (Protection Disabled)