Thanks a lot for your direction. I tried it out and everything's now PERFECT.
Here's the new master code with only a little change, even simpler than before:
sbit master_sck_direction at trisc3_bit;
sbit master_sdi_direction at trisc4_bit;
sbit master_sd0_direction at trisc5_bit;
sbit master_ss_direction at trisd1_bit;
sbit master_ss at rd1_bit;
void main() {
char send=3;//could be anything, prefarably '\0' instead.
master_sck_direction=0;
master_sdi_direction=1;
master_sd0_direction=0;
master_ss_direction=0;
master_ss=1;//slave deselected at start
uart1_init(9600);
spi1_init_advanced(_SPI_MASTER_OSC_DIV4,_SPI_DATA_SAMPLE_MIDDLE,_SPI_CLK_IDLE_HIGH,_SPI_HIGH_2_LOW);
while(1)
{
if(rcif_bit)//VERY IMPORTANT IF NOT AFTER FIRST KEYBOARD PRESS, TRANSFER WOULD CONTINUE INDEFINITELY. IF REPLACED BY (!rcif_bit), NOTHING WOULD EVER BE SENT.
{
send=uart1_read();
master_ss=0;//select slave
spi1_write(send);
master_ss=1;//deselect slave
delay_ms(50);
}
}
}
/*
Here's a very important piece from the datasheet of 16f877a explaining why i encountered the problem. It states:
"If enable bit SREN is set, then only a single
word is received. If enable bit CREN is set, the reception is continuous until CREN is cleared. If both bits are
set, CREN takes precedence. After clocking the last bit,
the received data in the Receive Shift Register (RSR)
is transferred to the RCREG register (if it is empty).
When the transfer is complete, interrupt flag bit, RCIF
(PIR1<5>), is set. The actual interrupt can be enabled/
disabled by setting/clearing enable bit, RCIE
(PIE1<5>). Flag bit RCIF is a read-only bit which is
reset by the hardware. In this case, it is reset when the
RCREG register has been read and is empty."*/