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PIC SPI with interruptions

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Hello everybody and thanks

I have developed a system that uses two PICs that communicate through SPI. Therefore a master and a slave. I am planning to try next a master and several slaves. As you know communication can only be started by the master with the slaves responding.

However, the master polling its slaves would take resources, so instead how about interruptions? I mean, when a slave finish its task and is ready to transmit, notify the master through interruptions

Have you ever heard about this? How do you do this? So far I am thinking some cables communicating the slaves to a general IO of the master and generating those kind of interruptions. But that would take a lot of pins if the slaves are several (and plus we also use pins to activate SS!)

Does anybody have an advice on this?

Thanks
 
One or many implies a pull up resistor.
And even then when two or more pull that pin down the Master just learns that "one or more " are ready for something.
 
I would implement the signal on the CS line.... As only a intelligent SPI slave would need serviced, I would have the CS pins on an IOC pin when waiting for a response, tri state the CS pins and then you will know which device is signalling...
 
Thanks Ian I think your reply is very interesting but could you elaborate please?

I would implement the signal on the CS line....
Ok, but the CS line is unidirectional from Master to Slave no?

As only a intelligent SPI slave would need serviced,
Yes, I suppose we can assume only a few of the set of slaves would need that

I would have the CS pins on an IOC pin when waiting for a response, tri state the CS pins and then you will know which device is signalling...

You lost me here...:confused: you would put the (Master) CS pins on a (Master?/Slave?) IOC (Interrupt on change I guess) pin...??? , tristate (so change the pin direction from output to input) the CS pin... and then...?


Oh wait... you mean you would use as (Master)CS oins the few pins of the chip that are IOC (for my chip they are RB4~RB7), then tristate the pin? What does this mean exactly? I am guessing some change of direction .... nah I think I still need some explanation:banghead:
 
Wait, I think I am little by little understanding what you mean... please tell me if I am wrong

You mean, to use as CS pins the IOC pins of the master (in my case RB4~RB7), and instead of setting them as output all the time (as I do know with TRISB=0), setting them as input (TRISB=1). (That would mean tristate the pins). Obviously with that configuration they can't be used as CS so whenever I have to use them as CS, only then put them as output (TRIS=0) , select the slave, transmit, receive and when finish, not only unselect the chip (by putting CS=1) but also turn them again to input (TRIS=1).

Meanwhile, when the slave finish and needs service, it will send some signal through those lines and since CS is input, the master will sense that thorugh IOC interruption and service it (by doing what I wrote above)

Is that what you meant?


If this is so, the only issue I still got is
what happen to the SS pin on the slave? If we have configured it with SSPM3~0 as 0100 then can we suddenly use this pin as output as well???
 
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I am a little confused. I know that theoretically SS is used to "select the slave".

But when does the slave checks if it is "chosen" or not? I dont see it. Or is it automatically? Yeah I think it is automatically.

So if I don't use SS, just leave it as a general pin, I have to check this in my code right??? it is not automatically anymore, am I wrong?
 
Okay!!!
You have control of the slave.... When you are processing, disable communications until you are ready to send..
make the SS pin an output and give it a pulse.. Then set the pin to input and re-enable SPI .. By the time the master has read the interrupt and decided which slave is ready the slave will be ready to talk!!
 
You can do this if you make sure the idle state is high on open drain outputs with pull-ups on slave outputs and the CS line port pin so it can used for slave select or slave interrupt (high to low edge/level trigger) to the master tied to a PORTB interrupt on change input/output CS pin. Some simple logic might be needed to gate out master transmit data to other devices received during slave requests on it's receive line (data received during this overlap time by the slave will be discarded while the slave output remains high to avoid collisions) if timing is ad-hoc.

Unless pins/connections were limited I would just use a separate request output pin on the slave with a dedicated wire to a master service interrupt input pin.
 
I put everything on a breadboard, tried it and it works almost great...
so I decided to put it on a perfboard
well... now the transmission sucks, the slave sends garbage or 0x00 etc .
Now, I have checked the connections, it seems there is no mistake
so the only thing I can think of is

do SPI fail if I use this extremely thin lead wires to connect it as in (pardon the ugliness)
OpenCVCapture.jpg

when it was working on the breadboard I use normal awg wires or jumper wires say 24 or so.
Now with this it is not working..

Any idea or comment please?
 
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