PIC pins linked??

[Oznog]

I have done a number of complex PIC projects with the PIC18252/452. I am having trouble with a new project on the PIC18F452 at a very simple level. I code in C, but checked the assembly code too.

I am seeing pin E2 is somehow cleared by a bit clear to E1. I rewrote a very simple piece of code to explore the problem.
03BA bsf PORTE,2
03BC bcf PORTE,1
03BE bsf PORTE,1
03C0 bra 0x3BA

This is causing E2 to clear along with E1 when "bcf PORTE,1" executes. E2 has a square wave with a duty cycle of what looks like 1/4. The board definitely does not connect these pins together, and TRISE=0x00. There is nothing in the interrupt routine which deals with portE, and in any case no interrupts are enabled.

I have tried this with different PIC18F452 chips and the results are the same.

I'm stumped. Any ideas?

 

[Exo]

Seems like the read-modify-write bug to me.
18F series pic's have extra registers to solve it, called LATX (where x is the port). But I don't have much expierience with it, perhaps you should post the question on the forums of microchip themselves, they know more about RMW then me.

 

[Andy_123]

Try
03BA bsf LATE,2
03BC bcf LATE,1
03BE bsf LATE,1
03C0 bra 0x3BA

 

[Oznog]

Yeah, I ended up doing that. It does make it work, but I don't understand why, and that troubles me.

I heard an explanation awhile back that the difference between LAT and PORT only comes up if you do a read, modify, and write on a port with a tristated pin. The tristated pin would read the digital value of the input voltage on it and write it back to the internal latch and that would be reflected if the pin's tristate bit was cleared.

I don't even have tristates on this port so it's hardly the case. What's up here?

 

[Exo]

It has something to do with slow rise and fall times of a pin. A read-modify-write reads the entire register of the pins real status, modifies the bit, and writes it back again.
Now, if you set a certain bit and for some external reason it takes a couple of µS for the pin to actually rise or fall (capacitance,... ?), then the next instruction will be executed while that pin hasn't reached the desired state yet. Reading it by a RMW instruction will read the faulty state.

I believe it was something like that. I'm sure the guys at the microchip forums can explain it better.