PIC clock control ??

[patroclus]

Hello,

https://www.electro-tech-online.com/custompdfs/2004/09/Bs11-1PDF.pdf

Could anyone explain me what exactly happends in 74HC47?? (lower right).
The PIC supposely controls the clock behaviour through RB3 (the web says it is a 3 states I/O pin), but D is an output, isn't it? and Q is conected to inputs (it clocks the rest of integrated circuits).

Some light over here?
thanks.

 

[Nigel Goodwin]

Hello,

https://www.electro-tech-online.com/custompdfs/2004/09/Bs11-1PDF-1.pdf

Could anyone explain me what exactly happends in 74HC47?? (lower right).
The PIC supposely controls the clock behaviour through RB3 (the web says it is a 3 states I/O pin), but D is an output, isn't it? and Q is conected to inputs (it clocks the rest of integrated circuits).

Some light over here?
thanks.

The lower right chip is a 74AHC74 (not a 47), have you perhaps looked up the wrong number?.

 

[patroclus]

Yes, 74AHC74. I made a mistake writing
Anyway, what does it really do?

 

[Optikon]

Hello,

https://www.electro-tech-online.com/custompdfs/2004/09/Bs11-1PDF-2.pdf

Could anyone explain me what exactly happends in 74HC47?? (lower right).
The PIC supposely controls the clock behaviour through RB3 (the web says it is a 3 states I/O pin), but D is an output, isn't it? and Q is conected to inputs (it clocks the rest of integrated circuits).

Some light over here?
thanks.

OK,

This part is a "D" flip flop. The D is the input and it transfers that to Q on the rising edge of the clock (which is doubled). The part also provides NOT(Q) as well.

I believe the RB3 pin is used to turn off the clock or let it run. based on whether or not it is in high-Z or ground. The Q and not-Q are just doubled clocks running the other circuits. The way it works is this:

Assume Q is high, then not-q will be low. not-q is fed back to the D-input. When the next clock edge comes, it will transfer to the output q, so now q is low which means not-q is now high. This again gets fed back to the d input and the circuit toggles like this hereafter synchronous to the input clock(signal generated by that XOR).

To stop this behavior, pull RB3 low. So now, the feedback on the flip flop won't have any effect on the D input and on the next primary clock(the clock input ot the FF) the Q output will go low and Not-q will go high. They will sit at these levels (q clocks stopped) until RB3 goes back into 3-state (high-z) to enable the feedback behavior again.

So this flip flop just sort of buffers the doubled main clock with a stopping control feature implemented.

Which, by the way, this is not a good design practive to feedback on the flip flop like they do. I think it works well enough but there are better ways..

 

[patroclus]

Great, now I understand everything.
thank you

(by the way.. how could be done better? if it is more complicated then I preffer this way as it seems to work quite well up to 50 Mhz clocks).