If for example you set _INTRC_OSC_CLKOUT in the configuration word then you typically end up with a clk/4 signal from the CLKOUT pin. In what sort of real-world circumstances is this useful ?
Is it divided by four?, I've never looked at the internal oscillator operation for this, but one use for it is to use one crystal for two PIC's, with the output from one feeding the input on the other.
That's my biggest gripe with PIC's and why I love the AVR architecture so much. AVR's run at the clock speed, no divider. The instruction pipeline is paralleled, which means it can be 4 times faster for a given clock rate.
It would be useful for a PIC if you needed to time an external circuit to occur at the same clock cycle as the instruction pipeline, not the native clock. I'm sure the external clock is generated during a specific cycle of the Instruction clock for the pic, perhaps to allow high precision timeing with an external circuit.
That's my biggest gripe with PIC's and why I love the AVR architecture so much. AVR's run at the clock speed, no divider. The instruction pipeline is paralleled, which means it can be 4 times faster for a given clock rate.
Presumably the AVR uses a clock multiplier?, like the 18F series does, which runs at the external clock rate as well.
How long are AVR instructions?, and how many instruction cycles do they take?, 16F PIC ones all single word, and almost all take only a single instruction cycle. The 18F gets more complicated, with some double word instructions.
The AVRs are quite impressive, typically running at 20MHz and with instruction times of 1 cycle. I haven't used them yet but am thinking of getting a dev kit to have a play. Have a look at the ATtiny13 an 8 pin 20MIPS chip with 10bit ADC.
No Nigel, the processors architecture is such that it is fetching the next instruction while the current one is executing, so it's instructions are executed at the clock speed. Word and multiplication instructions take 2 cycles. Jumps go from 2-4 clocks. Most memory instructions are 2 cycle. It's greatest advantage over PIC's is in basic arithmetic operations and I/O instructions are all single cycle. Go to Atmel's site and grab the Instruction Set summary if you want, it tells the length of each instruction.
Optimized AVR code can be up to 4 times faster or 4 times the resolution of PIC code.
Actually AVR's typically run at 16mhz, 20mhz is not as common. I've heard some reports of moderate over clocking success but at that point the flash read times hold it back.
There are a few AVR's that have PLL modules for high speed PWM (100khz 8 bit duty cycle) basically for motor control or buck/boost applications.
No Nigel, the processors architecture is such that it is fetching the next instruction while the current one is executingQUOTE]
Don't most processors do that anyway?, I'm pretty sure the PIC does?, and the ancient 6502 certainly did.
However, pre-fetching the next instruction doesn't mean the processor runs at the external clock speed, processors which don't do it tend to require a MUCH faster external clock than those that did (such as Z80 vs 6502).
Then it's just the way the instruction cycle is pipelined, though there are options for running a prescaler if you need to slow the chip down (to reduce power), and the ones with the high speed PLL can run from a divided high speed PLL clock. It's one of the things they pride their chips on (1MIPS per Mhz)