PIC ADC Interrupt Timing?

[Mike - K8LH]

Gentlemen,

Would you double check my logic please? I'd like to perform ADC conversions at 20-usec intervals (50-KHz) within an ISR using TMR2 interrupts.

;
;  ADC PWM processing (PWM pulse skipping algorithm)
;
ISR_ADC
        bcf     PIR1,TMR2IF     ; clear TMR2 interrupt flag       |B0
        movlw   DutyCyc         ; normal duty cycle value         |B0
        movwf   CCPR1L          ; assume VADC < VSET              |B0
        movf    VSET,W          ; voltage set point               |B0
        subwf   ADRESH,W        ; ADC result hi                   |B0
        skpnc                   ; VADC < VSET                     |B0
        clrf    CCPR1L          ; VADC > VSET, skip pulse         |B0
        bsf     ADCON0,GO_DONE  ; start next ADC conversion       |B0
        retfie                  ;                                 |B0
;

I'm assuming that after setting the GO_DONE bit in the ISR that a conversion will take place and that the next ADC acquistion period will be fullfilled by the time the next 20-usec interrupt occurs.

Will this work?

TIA. Regards, Mike

 

[Pommie]

I don't completely understand what you are trying to do but I did notice that the movf VSET would default to placing the value back into VSET, is this what you intended? Also, if you previously had a value of zero in CCPR1L then any write will be immediately latched into the PWM module (I think).

Mike.

 

[Mike - K8LH]

Hi Mike,

I fixed that movf instruction. Thanks for catching it.

The TMR2 interrupt is the same as the PWM period match when the previous CCPR1L change takes effect.

 

[Pommie]

Now I have had time to figure out what you are trying to do, I think your logic is fine. I'm not as sure about your timings. TAD (conversion time per bit) has a minimum of 1.6uS (typically 2.0) and it takes 11 per conversion = 17.6uS + 2*TAD after conversion. The sample and hold capacitor is disconnected during conversion and when reconnected requires around 19uS acquisition time.

So, I think your scheme will work but at about half your current speed.

BTW, is this some sort of SMPS design. If so, I would be very interested in your results.

Mike.
P.S. I'm assuming 16 series.

 

[Nigel Goodwin]

My first thought is you aren't saving and restoring any registers?, so it's soon going to crash - as an ABSOLUTE MINIMUM you must save W and STATUS.

 

[Pommie]

My first thought is you aren't saving and restoring any registers?, so it's soon going to crash - as an ABSOLUTE MINIMUM you must save W and STATUS.

Or, your main code is

Here        goto   Here

Mike.

 

[Pommie]

On a more serious note, I have in the past had my main loop test a bit which is set by the IRQ and not bothered with the context saving as it makes the IRQ response quicker. I assume Mike K8LH has done something similar.

Mike.

 

[Nigel Goodwin]

On a more serious note, I have in the past had my main loop test a bit which is set by the IRQ and not bothered with the context saving as it makes the IRQ response quicker. I assume Mike K8LH has done something similar.

Presumably you mean polling the output of the timer?, and NOT using interrupts - this isn't what he's doing though, and his ISR routine certainly destroys W and STATUS.

 

[Pommie]

Presumably you mean polling the output of the timer?, and NOT using interrupts - this isn't what he's doing though, and his ISR routine certainly destroys W and STATUS.

No, I mean polling a bit set by the IRQ code. As long as the test in the main code is a btfss/c then you can destroy W and Status in the IRQ and your main code will work fine.

Mike.

 

[Nigel Goodwin]

No, I mean polling a bit set by the IRQ code. As long as the test in the main code is a btfss/c then you can destroy W and Status in the IRQ and your main code will work fine.

No it won't, even if your main code does nothing else except BTFSS/C (which it can't), destroying STATUS will probably alter the outcome of the test anyway! (depending what you're testing).

The ISR routine shown destroys both W and STATUS, so you can't use either of those in your main program - because you never know when they are going to be altered.

 

[Mike - K8LH]

My first thought is you aren't saving and restoring any registers?, so it's soon going to crash - as an ABSOLUTE MINIMUM you must save W and STATUS.

Hi Nigel,

I knew I should have qualified that code (grin).

Aside from the initial setup, the Main program simply performs an endless loop and the ISR does all the real work of handling bit-banged SPI input and that ADC-to-PWM control loop.

Mike

 

[Mike - K8LH]

Now I have had time to figure out what you are trying to do, I think your logic is fine. I'm not as sure about your timings. TAD (conversion time per bit) has a minimum of 1.6uS (typically 2.0) and it takes 11 per conversion = 17.6uS + 2*TAD after conversion. The sample and hold capacitor is disconnected during conversion and when reconnected requires around 19uS acquisition time.

So, I think your scheme will work but at about half your current speed.

BTW, is this some sort of SMPS design. If so, I would be very interested in your results.

Mike.
P.S. I'm assuming 16 series.

Hi Mike,

The code is for a 12F683 boost SMPS.

Thank you for the timing info'. I'm going to breadboard the circuit and start experimenting.

Mike

 

[Pommie]

Mike,
Have you considered using the comparator with Vref. It would only give you 16 (maybe 32) possible voltages but would be a lot faster. You would then also have the distinction of being the only person I have heard of to use the comparators.

Mike.

 

[Mike - K8LH]

Mike,

I did think about the comparator with internal Vref, but as you mentioned, it doesn't offer very much resolution.

I don't really know where the experiments will lead. It's just something I'd like to become more familiar with.

Take care. Regards, Mike