Phase Locked Loop

[tnecniv]

can the PLL achieve phase lock and not frequency lock?
and can the PLL achieve frequency lock and not phase lock?

Please advise. Thank You

 

[crutschow]

It is not possible to achieve one without the other. How could you?

 

[tnecniv]

From what i understand is that u can achieve phase not locked but frequency locked. as loop equation can give a constant(1st order PLL) or zero when calculated.
the derivatives of phase gives the frequency which is always zero in both case.

I just need to confirm if i am right to say a PLL can achieve phase not locked and frequency locked but not phase lock and frequency not locked.

 

[tnecniv]

It is not possible to achieve one without the other. How could you?

I think its possible rite? u can have 2 car travel at the same rate of change of speed. their distance will be maintained but that does not mean they are travelling at the same speed. Please advise if i am right.

 

[JimB]

When a PLL is in lock, the output is the same as, (or an integer multiple of, if there is a divider in the loop) the reference frequency.
The frequencies are the same.

The phase difference between the output and the reference will be constant at some value.
Depending on the loop design, there may be 0deg phase shift between the output and the reference, or there may be some fixed offset of a number of degrees.

JimB

 

[ronsimpson]

I have used the MC14046 or CD4046 PLL. It has several options. One is an edge lock detector. It will try to align two rising edges. (phase and frequency will be in lock) Another option is to lock the two frequencies together but will not lock the phase. This option will have the two signals 'locked' but the phase will not be the same. The phase will change with time.

There are many different types of PLLs. Phase comparator 1 of the 4046 (almost) requires the phase to not match. It is typical for the phase to be different by 90 degrees.

 

[tnecniv]

Thanks for the reply. From what i understand is that it PLL will always achieve frequency loop when PLL is in lock. Phase lock or no phase lock depend on settings.
This is the same as theoretical of PLL

 

[alec_t]

their distance will be maintained but that does not mean they are travelling at the same speed. Please advise if i am right.

That can't be right (at least, not in this universe) if by 'same speed' you mean their velocity vectors match both in magnitude and direction.

 

[crutschow]

By definition if the frequencies of two signals are identical (locked), then their phase must also be locked (fixed phase-difference between the two signals).

A multiplier type phase-detector can have a varying phase difference point at which it locks. But once it locks, the phase difference does not vary (unless the loop is unstable or the loop parameters change). If the phase varies over time, then by definition the relative frequencies are also slightly varying over time.