Phase Locked Loop Using Micro

[alisarhangpour]

I've tried to implement a complete phase locked loop in an atmega16, and got succeed to follow the 50Hz mains frequency.It works as follows:
A rising edge of the mains sine wave (converted into square wave) triggers an interrupt, a lookup table is used to make an internal sine wave, and interrupt service routine decides whether this internal sine wave is lagging or leading, and makes the pwm period longer or shorter.
But PLL works somewhat oscillatory, it doesn't stay fixed at, say, 50Hz. it goes around 49 Hz to 51 Hz. And it makes a dangerous phase difference. Probably because of a low resolution VCO, or bad designed transfer function.
Can anyone give a good algorithm for a microcontroller based PLL?
Thank You

 

[Nigel Goodwin]

No idea on Atmel, but your original premise sounds wrong? - it's normal to use a zero-crossing detector, not convert it to a squarewave.

 

[alisarhangpour]

The interrupt works as the zero crossing detector, I've just converted it into a square wave to detect its zero crossing easily using external interrupts, besides I'm not so stuck to Atmel, any idea which can be implemented using micros is appreciated.

 

[Leftyretro]

I've tried to implement a complete phase locked loop in an atmega16, and got succeed to follow the 50Hz mains frequency.It works as follows:
A rising edge of the mains sine wave (converted into square wave) triggers an interrupt, a lookup table is used to make an internal sine wave, and interrupt service routine decides whether this internal sine wave is lagging or leading, and makes the pwm period longer or shorter.
But PLL works somewhat oscillatory, it doesn't stay fixed at, say, 50Hz. it goes around 49 Hz to 51 Hz. And it makes a dangerous phase difference. Probably because of a low resolution VCO, or bad designed transfer function.
Can anyone give a good algorithm for a microcontroller based PLL?
Thank You

Well the basic premise of a PLL is one of a feedback system where the error detected is feed back for correction. If there was no error then the system would not function. Most PLL systems use some form of analog filtering after the phase detector to 'tune' the error response of the system. This error filtering and tuning is probably the most complex part of designing a good PLL system. Your PWM step resolution (10 bits?) will be one factor in the overall loop response but some form of digital filtering (averaging of multiple samples) may smooth out the response.

Lefty

 

[wschroeder]

If you don't detect the zero-crossing as accurately as possible, and are depending on a rising/falling threshhold value to create your signal, then you will have phase problems relative to the original signal. You have to lock-in on zero and not some threshhold value.

 

[mvs sarma]

If you don't detect the zero-crossing as accurately as possible, and are depending on a rising/falling threshhold value to create your signal, then you will have phase problems relative to the original signal. You have to lock-in on zero and not some threshhold value.

I think Detection of ZERO crossing can't be that accurate. Unless the paramater is of recognisible lebel after changing the direction, only then any hardware circuitry can respond. Thus it may be well after the zero croosing , not at the zero crossing.
As rightly indicated by Leftyretro, this observable oscillatory behavior can't be avoided if PLL is attampted at 50Hz.
The attempt by Alisarhangpour is appreciable and there and perhaps may form a good topic for debate.

 

[wschroeder]

There are a number of good zero-crossing detection circuits which are fast enough so that phasing differences relative to 50Hz are of no appreciable significance.

http://www.discovercircuits.com/XYZ/zerocross.htm

 

[eblc1388]

Well the basic premise of a PLL is one of a feedback system where the error detected is feed back for correction. If there was no error then the system would not function.

How about PLL configuration that locks at 90 degree phase difference between input and output?