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PCB design question

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e1ioan

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I'm designing the PCB for one of my projects and I have few questions:
Should I use pour planes on both sides? I wanted to link the bottom pour plane to GND and top pour plane to VCC. Any reasons I shouldn't do this? I know that this will make a big capacitor, will this capacitor help the filtering or will just give me unexpected problems? What about connecting top and bottom pour planes to GND, is this better design?

TIA
-ioan
 
I was going to ask the exact same question!
Instead of starting a new thread I guess anyone who responds will hit 2 birds at once.
Perhaps what the circuit is composed of will make a difference in such a decision, in my case it is a PIC generating 40KHz PWM how about you Ioan?

Mike
 
For high frequency designs and good decoupling I like lots of ground plane, so my design for a switching regulator, for example, had ground pour on the top middle, and bottom layers, tied together with numerous vias. That way the surface mount decoupling capacitors, which were mounted close to the power pins on each IC, are connected directly to the ground plane. To improve the decoupling effect of the capacitors I also tried to run the power trace directly through the other mounting pad of the cap, instead of using a T connection, wherever possible. That minimized trace inductance on both sides of the decoupling capacitor to essentially that of the capacitor package, which maximizes the decoupling ability of the cap. I did make the power traces wider than the signal traces to minimize trace power line impedance.

For low frequency or audio type circuits putting power on one layer and ground on the other should also work fine. The capacitance between the two layers will act like a small decoupling cap from power to ground.
 
Using a lot of copper, top and bottom, forms a capacitor, and that is good. It also uses up less chemicals if you are going to etch your own boards. It also helps spread the heat out. That is good, too. In higher frequencies it is almost mandatory to have big, stable pours to keep oscillations from finding places to live.
 
I have seen many examples of this. In theory, this also has the role of decoupling capacitors.
 
In four-layer board, there is a large area on the power layer and ground layer. I think reason is similar.
 
In my circuit I have 9 volts and 5 volts so I would have the bottom layer set to ground and should I have the top layer set to 9V or 5V? 9V goes to op-amps and 5V goes to PIC, piezo and LEDs.
 
Usually the 9V and 5V are dominant in their own areas. You don't have to use the entire area for a single voltage.

In my experience, in a two layer board the principal benefit of top-side (power) fill is conserving etchant.
 
e1 did not state what kind of circuit the pcb is for. For RF, use ground planes. Although a good design can get by without. For LF (to a few 100 kHz) it is not really needed.
I like my boards, especially protos, without ground-plane, as it is much easier to trouble-shoot through a translucent board. E
 
For high frequency designs and good decoupling I like lots of ground plane, so my design for a switching regulator, for example, had ground pour on the top middle, and bottom layers, tied together with numerous vias. That way the surface mount decoupling capacitors, which were mounted close to the power pins on each IC, are connected directly to the ground plane. To improve the decoupling effect of the capacitors I also tried to run the power trace directly through the other mounting pad of the cap, instead of using a T connection, wherever possible. That minimized trace inductance on both sides of the decoupling capacitor to essentially that of the capacitor package, which maximizes the decoupling ability of the cap. I did make the power traces wider than the signal traces to minimize trace power line impedance.

For low frequency or audio type circuits putting power on one layer and ground on the other should also work fine. The capacitance between the two layers will act like a small decoupling cap from power to ground.

Hi Carl, I was reading on the datasheet of some linear regulators that decoupling capacitors should not be connected by vias. Does that mean they should be on the same layer as the chip? ( Talking surface mount here )
 
Hi Carl, I was reading on the datasheet of some linear regulators that decoupling capacitors should not be connected by vias. Does that mean they should be on the same layer as the chip? ( Talking surface mount here )
That's the basic idea. Most of the time, it's desirable to execute a voltage regulator (linear or switching) design using a single layer, using vias only for external connections or heat sinking. Many switching regulator app notes will provide an example layout.

It's not always easy to communicate this to a layout person if they don't have a basic understanding of E/M fields.
 
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