Hi All,
I m new to building circuits and now I m trying to connect a 74HCT244 in between parallel port and uC AtmelMega8. The reason to this was a result of some googling that indicated that parallel port is of TTL logic which is not compatible with HiCMOS logic.
I use this as the datasheet for the buffer chip https://www.electro-tech-online.com/custompdfs/2008/12/SCHS167APDF.pdf.
One thing which is confusing me, is that will the buffer chip over-load my parallel port by pulling / sourcing more current. I am not able to see the maximum current flow provided in the datasheet for inputs at V(il) and V(ih). Can someone correct me in case I got the picture wrong.
Also, can someone point to some materials where the factors that are required to take into considerations while inter-interfacing of logic-levels needs to be done.
Thanks,
RAM
I m new to building circuits and now I m trying to connect a 74HCT244 in between parallel port and uC AtmelMega8. The reason to this was a result of some googling that indicated that parallel port is of TTL logic which is not compatible with HiCMOS logic.
I use this as the datasheet for the buffer chip https://www.electro-tech-online.com/custompdfs/2008/12/SCHS167APDF.pdf.
One thing which is confusing me, is that will the buffer chip over-load my parallel port by pulling / sourcing more current. I am not able to see the maximum current flow provided in the datasheet for inputs at V(il) and V(ih). Can someone correct me in case I got the picture wrong.
Also, can someone point to some materials where the factors that are required to take into considerations while inter-interfacing of logic-levels needs to be done.
Thanks,
RAM
