Output voltage a bit low and switching noise at high loads on this SMPS

[OutToLunch]

so, you still have the feedback in the same configuration as the schematic that you posted earlier? The system is unstable. You can see it with the oscillations on the output when the load is applied.

The output is also experiencing a 200mV drop when load is applied. For a 1A maximum load, this is significant. There could be a number of reasons why this is occurring, so I would address the stability issue first. Go back to my component suggestions post, make the changes and then retest.

Using ground planes and power planes is a good thing. They reduce parasitics, allow more current to flow and can help dissipate heat. I'm not sure what current loops around the MOSFETs you are refering to. Perhaps posting your layout for some review would benefit you as well.

 

[Optikon]

Ceramic capacitors, when used in conjunction with bulk capacitors, are generally placed at or as close to the point of load to provide immediate load support during a fast transient (i.e. high load current slew rates). The bulks are there to help support the rail while the inductor slews up. As far as needing them in this regulator, I don't see impementing them as hurting anything, but I don't think they're going to add much either. The output current maxes out at 1A - no transient this regulator will see will be enough to deplete the charge in the output caps prior to the inductor slewing up.

The capacitors we were discussing are for switching transient suppression NOT load transient.

Do you see those high frequency spikes in the scope plots (the very thin ones), those are switching transients.

 

[FusionITR]

Yes I still have the same configuration as before, I just was testing the current design to test what I should look out for when scoping in the future.

So when I apply a transient load, I should see no oscillation on the output, or as little oscillation as possible?

The curret loops I was referring to is the current loop to the source of the mosfet and the current loop from the drain of the mosfet. All other currents in the circuit should be insignificant.

Layout here: **broken link removed**

Download expresspcb to view it.

 

[Optikon]

Your 200mV drop could be from ESR and wiring resistance in your output path. It only takes 0.2 Ohms @ 1A.

 

[Optikon]

Yes I still have the same configuration as before, I just was testing the current design to test what I should look out for when scoping in the future.

So when I apply a transient load, I should see no oscillation on the output, or as little oscillation as possible?

The curret loops I was referring to is the current loop to the source of the mosfet and the current loop from the drain of the mosfet. All other currents in the circuit should be insignificant.

Layout here: **broken link removed**

Download expresspcb to view it.

You should see no oscillation if your system is stable. A little bit of oscillation / overshoot could indicate marginal stablility.

 

[Optikon]

High current loop MOSFET ON state: C2 & C6 -> Q1 -> L1 -> C9 -> GND -> C2 & C6



High current loop MOSFET OFF state: GND -> D1 ->L1 -> C9 -> GND

Minimize these loops physically by how you run wires & place parts to HELP reduce noise.

 

[Optikon]

Yes I still have the same configuration as before, I just was testing the current design to test what I should look out for when scoping in the future.

So when I apply a transient load, I should see no oscillation on the output, or as little oscillation as possible?

The curret loops I was referring to is the current loop to the source of the mosfet and the current loop from the drain of the mosfet. All other currents in the circuit should be insignificant.

Layout here: **broken link removed**

Download expresspcb to view it.

Sorry, I can't view it and not going to install software to do so. Noise-wise, I think you know how to layout your parts. Add the ceramics in th e right spots. I would investigate your stability problem further.

 

[OutToLunch]

The capacitors we were discussing are for switching transient suppression NOT load transient.

Placing ceramic capacitors on the output of the inductor won't improve the regulator. Transients due to the switching of the mosfets will occur at the phase node and occur due to parasitics in layout and in the mosfets themselves - not at the output of the LC filter. Ringing on the phase node, if considered to be excessive, can be damped with an RC snubber placed from the phase node to ground - good layout practices will also minimize ring as well.

Do you see those high frequency spikes in the scope plots (the very thin ones), those are switching transients.

Those spikes have nothing to do with the switching of the mosfets. Those spikes are due to the load transient. Spikes at the leading and trailing edge of a load transient are due to the parasitics of the output capacitor bank ESL and ESR. The speed at which the load is ramped up can be a major contributing factor to the magnitude of the spikes. Since many loads can slew up much faster than the regulator is switching, the only way to manage them (if they require management) is to reduce the parasitics. This is done through a combination of layout (large copper fills and planes to reduce any parasitic inductances from the board) and also increasing the number of output capacitors which will reduce the total parasitic inductance attributed to the leads and the internal structures of the capacitors. Another contributing factor to the initial spike is the total ESR of the output cap bank. Reducing the total ESR will reduce the size of the spike.
Spike magnitude can be estimated by:
Vspike ~ ESL*dIload/dt + Iload*ESR
Where ESL is the total parasitic inductance presence. Not something that can be easily measured, but can be estimated. The Iload*ESR portion is easily calculated, so if the spike is excessive and the ESR portion of it is not contributing significantly, then the parasitics inductances must be dealt with.

In this case, I don't believe there is anything to worry about. He is creating a load transient that likely has a very large di/dt which I would suspect is not representative of the load that will be serviced by the regulator. I have not reviewed his layout yet, but I would suspect that improvements in that area would likely help reduce those spikes as well.

 

[OutToLunch]

The layout has some issues that are definately causing problems.

All the high current paths that you had are made with 25 mil traces. The trace from the input voltage connector to the capacitors may work, but it's not adviseable. At least the capacitors were tied to the plane. The connection between the MOSFET and the diode is made with a 25 mil trace and then from the diode to the inductor as well. Same is true for the connection to the output connector.
Original Top Layer:
**broken link removed**

The following images show proposed changes to the layout.
*The bottom layer is still a ground plane, but there is a gate trace from the PWM IC to the MOSFET routed in it.
*I got rid of the input voltage plane on the entire top and replaced it with a copper fill that is directed only to the places that require it.
*I flipped over the FET and moved the input caps so that everything is close together with respect to the input rail
*The ground traces for the input and output capacitors were widened and an extra via was added (not really necessary for a 1A design, but it can't hurt)
*The Drain of the FET, the cathode of the diode and the inductor are connected with a large copper fill. The anode of the diode is tied to the ground plane with a fatter trace and two vias.
*The inductor, output capacitors and output connector are tied together with a large copper fill.
*The feedback path is connected right at the output connector pin.
*I removed R5 and moved R4 to be between the VFB pin and Ground.
*Comensation components were rearranged cuz I'm anal
Top Layer Edit:
**broken link removed**
Bottom Layer Edit:
**broken link removed**

Since the max output current is only 1A, the MOSFET and diode are way oversized. This could be done with smaller packaged components and the layout could be compressed to make the board much smaller.

 

[Optikon]

Placing ceramic capacitors on the output of the inductor won't improve the regulator. Transients due to the switching of the mosfets will occur at the phase node and occur due to parasitics in layout and in the mosfets themselves - not at the output of the LC filter. Ringing on the phase node, if considered to be excessive, can be damped with an RC snubber placed from the phase node to ground - good layout practices will also minimize ring as well.

Those spikes have nothing to do with the switching of the mosfets. Those spikes are due to the load transient. Spikes at the leading and trailing edge of a load transient are due to the parasitics of the output capacitor bank ESL and ESR. The speed at which the load is ramped up can be a major contributing factor to the magnitude of the spikes. Since many loads can slew up much faster than the regulator is switching, the only way to manage them (if they require management) is to reduce the parasitics. This is done through a combination of layout (large copper fills and planes to reduce any parasitic inductances from the board) and also increasing the number of output capacitors which will reduce the total parasitic inductance attributed to the leads and the internal structures of the capacitors. Another contributing factor to the initial spike is the total ESR of the output cap bank. Reducing the total ESR will reduce the size of the spike.
Spike magnitude can be estimated by:
Vspike ~ ESL*dIload/dt + Iload*ESR
Where ESL is the total parasitic inductance presence. Not something that can be easily measured, but can be estimated. The Iload*ESR portion is easily calculated, so if the spike is excessive and the ESR portion of it is not contributing significantly, then the parasitics inductances must be dealt with.

In this case, I don't believe there is anything to worry about. He is creating a load transient that likely has a very large di/dt which I would suspect is not representative of the load that will be serviced by the regulator. I have not reviewed his layout yet, but I would suspect that improvements in that area would likely help reduce those spikes as well.

The spikes are not only caused by load transient. The output capacitor must be re-charged at the switching rate which is a ..... switching transient.

The original capacitors the OP was considering placing in the design were in fact in the output because, regardless of the origin of the noise, THERE WILL BE noise conducted from this converter. It can in fact be filtered / snubbed which is what he was trying to do. (read original posts about insanely accurate output voltage) This is why the discussion turned to trying to minimize noise instead.

 

[OutToLunch]

The spikes are not only caused by load transient. The output capacitor must be re-charged at the switching rate which is a ..... switching transient.

Next time you are analyzing the response of a converter to a load transient take a very close look at the initial spike in relation to the load current. The leading/training edge spike lasts only as long as the load current is slewing up/down. These spikes are attributable only to load transient edges.

A good example of this can be seen on page 5 of this application note...
https://www.electro-tech-online.com/custompdfs/2006/07/an9932.pdf