# Oscope - Roman Black's Two Transistor Switcher Design

Discussion in 'General Electronics Chat' started by Jony130, Aug 2, 2012.

1. ### Jony130Active Member

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Because the old thread was closed at the time when I was writing this post. So I decided to start new thread.

http://www.electro-tech-online.com/...an-blacks-two-transistor-switcher-design.html

The circuit that I build on the breadboard look like this

First the voltage at Q2 base for C1 = 4.7nF; C2 = 1nF ; L = 3.3mH

Q2 base voltage for C1 = 4.7nF; C2 = 2nF ; L = 3.3mH

Voltage at Q2 base without C1 capacitor
As we can see without C1 circuit operate at at a higher frequency.

Next I change the coil inductance from 3.3mH to 220μH

Voltage at Q2 base when L = 220μH
As we can see the osculation frequency has change again.

And I also measure the voltage across coil terminals and the current that is flow through the coil. I measure the coil the current via 1Ω series resistor.

That all I have for now.

2. ### MicksterWell-Known Member

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As much as we sometimes like to continue debates, especially when hotly-contested threads become closed, we have to respect the moderation team's reasons for doing so.

New threads, along the same vein, usually tend to incite the same or similar responses and inevitably become locked too.

3. ### skyhawkNew Member

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Jony, thank you so much for sharing your data. I find it very interesting.

While I am disappointed that the frequency was not cut in half by doubling the value of C2, I am glad to see a large shift in contrast with a previous report. I wonder if any of the deviation from the simple theory could due to tolerances in the values of the capacitors. Do you have a capacitance meter that you could use to measure actual values?

Do you know or can you measure the resistance of your inductors? That would be valuble information in analyzing your results.

I am unsure of your vertical scale. Can you tell me the values of the voltage at the bottom of the downward spikes for each of your cases?

Thanks again,

Skyhawk

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5. ### skyhawkNew Member

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I apologize if I am going against moderators wishes. The results are tantalizing!! I would love to have more data.

6. ### MicksterWell-Known Member

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I'm not saying that you are going against the wishes of the mod/admin team, I'm just fore-warning that this thread could likely be deemed a continuation of the thread which became locked, and could subsequently become locked too.

There are probably quite a few more of our members who were saddened that the in-depth analysis got cut short.

Last edited: Aug 2, 2012
7. ### JimBSuper ModeratorMost Helpful Member

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Jony

Excellent stuff.

JimB

8. ### ericgibbsWell-Known MemberMost Helpful Member

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hi Jony,
Nice results.

Although I am a supporter of simulators and consider they are a very useful tool for analysing circuits, wherever possible, its essential that a final hardware test is carried out to verify the simulation results.

I use simulations often on the Forums, I find it easier to explain and discuss circuits with OP's by using images rather than a totally text explanation.

Like most people I find that by looking at picture or plot I can quickly take in the information.

Eric

OT: If we can keep this thread on track it will be an interesting discussion.

9. ### Mr RBWell-Known Member

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Jony, the period of the time delay is given by RZ charging both C1 and C2 together in parallel, until C1 voltage reaches 5.6v.

The reason C2 has a larger effect on the time delay (as Skyhawk said) is because with a larger value of C2, it causes C1 to be discharged to a lower voltage during the turn-off phase of the buck. This I think was Skyhawk's premise regarding the "timing" being controlled by C2.

However in my design there is an optimal discharge voltage for C1. If C1 is discharged too much it places a larger -Vbe voltage on Q1 regulator transistor, which is not good for reliability as small signal NPNs do not like a large reverse voltage b-e.

And if C1 is not discharged far enough, the overall delay time is reduced, and to compensate it is necessary to use a higher resistance for RZ, which will start to compromise zener current and Q2 base current, both hurting SMPS efficiency and regulation.

I settled on a C1 discharge range of 5.6v-3v, as being optimal. This discharge of 2.6v gives only 2.0v -Vbe, quite safe for Q2, but the 2.6v differential is enough to give a reliable time delay for later charging.

My recommendation to increase the RC delay is to increase both C1 and C2 as a pair keeping them in roughly the same ratio of C1:C2. So RZ is not changed, maintaining the required Z and Q2 currents, and the only thing changed is the total delay time.

As for the time delay principle, there are two factors;
1). The amount C1 is discharged is based on the size of C2 (compared to C1) AND on Vin. If either is larger C1 will be discharged further.
2). The actual RC delay that affects the SMPS freq is based on the distance C1 has to charge and the RC constant based on RZ into both C1+C2 in parallel.

Note that if the Vin is changed significantly the ratio of C1:C2 needs to be altered to again put C1 discharge delta back in the optimal 2.6v range. The C1:C2 ratios in my circuits were chosen to suit the expected Vin range (like the automotive range 11v-14.5v).

Both the inductor AND the RC delay period have an effect on frequency so doubling the RC delay period won't halve the frequency. Also, C2 changed by itself won't have a perfectly linear effect on the total RC time, even though it has a larger effect on the RC period than C1 does as you said.

If the RC delay chosen is too large, the freq is slowed too much and the inductor pushes close to saturation causing poor efficiency. A good balance of RC delay can be found where the L1 current ripple is reasonably low, and near this point the inductor has quite a large effect on frequency, maybe responsible for 60%.

10. ### MrAlWell-Known MemberMost Helpful Member

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Hi guys,

Oh a new thread? Nice. We can discuss this like humans

Would you like to see a new experiment in action that helps to verify the operation principles of this circuit?
1. Run the simulation with load as usual, note the output voltage (should be around 5v) and waveforms.
2. Disconnect the emitter of Q2 from the circuit.
3. Connect a 5v battery between the emitter and ground, positive side to the emitter.
4. Run the simulation.
5. If the output voltage is lower than 5v DECREASE the 5v battery voltage very slightly. If the output voltage is higher than 5v INCREASE the 5v battery voltage slightly.
6. Repeat 4 and 5 above until you get very close to 5v output, then note the waveforms.

This i believe shows that the emitter feedback mechanism is a much slower process than the Q1 collector current turn off mechanism so it cant be responsible for the cycle to cycle operation, but over a longer time period acts to regulate the voltage by changing the current through Q2 which changes the drive current to Q1 and thus the peak inductor current,.

Try if if you like and see that the waveforms are similar with or without the battery. Please note though that the battery has to be set at the right voltage or else the output will not be the same as with true voltage feedback so the waveforms would be somewhat different.

11. ### ericgibbsWell-Known MemberMost Helpful Member

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hi Al,

Here are the results of your procedure.

Note two images,

1st shows the time to steady state of the 5Vout and the 2nd the waveforms at the steady state.

Eric

12. ### Jony130Active Member

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My fluke show 4.86nF for 4.7nF capacitor and 1.01nF and 0.98nF for C2 capacitor.
Because I use two parallel capacitors to get 2nF.

For 3.3mH (measured 2.89mH and DC resistance 9.4Ω)

In all my pictures I use 1V/div and this blue marker (1) in the lower left corner on the vertical line show 0V line.

13. ### skyhawkNew Member

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Thank you Jony. I appreciate your help.

14. ### skyhawkNew Member

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Let me start off by saying that I came across this regulator on Roman's site several years ago and liked it very much. I intended to incorporate it into boards I built instead of a 7805 regulator. As will happen, I got busy doing other things and gave up hobby electronics. This discussion has rekindled my interest in the design.

My previously presented formula was based on the simplification of a constant slope ramp up of the base voltage on Q2. Since that was not creating results in agreement with measured values, I went ahead and did the full calculation based on solving an ode. I will not include the details here, but I will be glad to provide them to anyone interested. The final results are:

Toff = -Rz*(C1+C2)*lnY where Y = (Vin-Vref)/(Vin+δ-Vref) and Vref is the Zener voltage and δ is approximated by Vin*C2/(C1+C2).

Using the "more refined" formula with Vin = 14V, Vref = 5.6V, and Rz = 10K I obtained the following:

with C1 = 4.7nF and C2 = 1.0 nF, δ = 2.46V and Toff = 14.6μs
and with C1 = 4.7nF and C2 = 2.0nF, δ = 4.18V and Toff = 27.1μS

which is not much different from the results obtained with the simple equation but which disagrees with the measured values.

Next I took the voltages measured by Jony and plugged them into the formula and obtained 13.6μs and 24.9μs respectively. If I am reading Jonl's horizontal scale correctly the correct values are 23μs and 35μs.

The one thing that I notice with Jony's results is that the voltage build up flattens out more than I would expect based on the time constant before the switch on pulse. This flat portion seems to be extending the off time more than is predicted by the modeling. The measured values are both 9 to 10 μs longer than expected.

Note that the calculated values for δ agree well with the measured values from Jony's plot. They are approximately 2.4V and 4.0V respectively.

Last edited: Aug 3, 2012
15. ### skyhawkNew Member

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I appreciate Roman's discussion of the practical limits on the C1 discharge, what I call δ. The thing that I find interesting is that for the range of values being considered here the effect of the sum C1+C2 in the time constant is almost exactly compensated for by the effect of C1+C2 on δ even in the more rigorous calcultion of Toff.

16. ### skyhawkNew Member

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I wonder whether the flattening seen in the ramp up of the base voltage of Q2 in actual hardware vs simulation could be due to the Zener beginning to conduct and steal current from the capacitors just a little bit before the voltage is high enough to turn on Q2 thus extending the delay beyond the calculated value. Is there a way to test this hypothesis?

17. ### MrAlWell-Known MemberMost Helpful Member

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Hi,

What are you trying to prove here?

18. ### Jony130Active Member

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Excellent stuff skyhawk.
Also kept in mind that my input voltage was 12V instead of 14V and though I use 5.6V Zener diode, but still my output voltage was only 4.6V.
And I try to do some more measurement in the Sunday

He what to know why real world measurement not entirely agree with his calculations.

Last edited: Aug 3, 2012
19. ### skyhawkNew Member

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I'm operating from a belief (perhaps naive) that if I can predict the various voltage levels and times/frequencies for the circuit from component values and operating conditions then I have proved (at least to myself) that I understand how the circuit works, no ifs, and, or buts. Also, with the correct equations in hand I can design a circuit for other operating conditions or to use components I have available and have confidence it will work as desired.

20. ### MrAlWell-Known MemberMost Helpful Member

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Hi there,

Oh ok, well that is perfectly understandable and makes a lot of sense. But what kind of mathematical model are you using for the transistors?

There's a couple things you'll have to keep in mind though just in case you arent already...
For one, the gains of the transistors are almost never represented correctly in spice, and spice is after all a mathematical model already. If you have 100 transistors at home in a bin and you pick out one of them for say Q1, it wont have the same gain as the next one picked out of the bin, and it surely wont match the mathematical model unless you can make measurements and modify the model as per each individual transistor pulled out of the bin.
Q1's gain affects the turn off point and Q2's base emitter voltage and gain affects Q1's base current, so those things have to be taken into account.

The experiment Eric did was supposed to show how the emitter of Q2 was only responsible for long time period changes, but he didnt show the two circuit waveforms just the one set for some reason (maybe he had shown it in another thread). I'll ask him.

Eric:
I thought the experiment was going to be to compare the two circuit waveforms side by side, ie with no battery (connected normally) and then with the battery instead of the emitter connected to the output?
Can you show the waveform with and without the battery? I think that would do it. They should be similar.

Last edited: Aug 4, 2012
21. ### Mr RBWell-Known Member

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Very cool effect! Thanks MrAl and EricGibbs for testing that, it's interesting to see it will still oscillate based on collector current (collector saturation) of Q1 plus possibly some inductor saturation effect in there too.

However I think this will require higher peak inductor current (with the associated loss in efficiency) and of course the very real issue that there is no load regulation!

In one of my early tests before this design I had an extra resistor of 1 ohm or so between the inductor output and the load cap. Feedback was taken from the front of the resistor to Q2 base, so there was a much larger voltage ripple to activate Q2.

Once the RC delay was added there was no longer a need for the load voltage to have ripple to give a reliable low freq oscillation.