# open drain output.

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#### alphacat

##### New Member
Hello.

In my USB-to-UART chip, CP2102, it is said that:
"
the reset pin, an I/O Device Reset pin, is an Open-drain output of internal POR or VDD monitor.
An external source can initiate a system reset by driving this pin low for at least 15 μs.
"

Could you explain please what does it mean an open drain output?

I connected this pin to the RST pin of my MCU (both pins are connected to a RST switch with pull-up resistor), and I noticed that every power-up, the CP2102 RST pin causes a HW reset to the MCU RST pin, and I was told that it got something to do with the "open drain output" issue.

Thank you for any help.

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#### ericgibbs

##### Well-Known Member
Hello.

In my USB-to-UART chip, CP2102, it is said that:
"
the reset pin, an I/O Device Reset pin, is an Open-drain output of internal POR or VDD monitor.
An external source can initiate a system reset by driving this pin low for at least 15 μs.
"

Could you explain please what does it mean an open drain output?

I connected this pin to the RST pin of my MCU (both pins are connected to a RST switch with pull-up resistor), and I noticed that every power-up, the CP2102 RST pin causes a HW reset to the MCU RST pin, and I was told that it got something to do with the "open drain output" issue.

Thank you for any help.
hi,
An open drain is the same as an open collector.

All it means there is no INTERNAL pullup or pulldown resistor on the pin, an external resistor is required.

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#### alphacat

##### New Member
hi,
An open drain is the same as an open collector.

All it means there is no INTERNAL pullup or pulldown resistor on the pin, an external resistor is required.
Thank you

It is said that this is open drain output.
How does it settle with the fact that each time I power-up the CP2102 device (USB-to-UART bridge), this RST pin causes the MCU's RST pin to go LOW and then HIGH - causing the MCU to have a HW reset?

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#### ericgibbs

##### Well-Known Member
Thank you

It is said that this is open drain output.
How does it settle with the fact that each time I power-up the CP2102 device (USB-to-UART bridge), this RST pin causes the MCU's RST pin to go LOW and then HIGH - causing the MCU to have a HW reset?
Code:
the reset pin, an I/O Device Reset pin, is an Open-drain output of internal POR or VDD monitor.
[B]An external source can initiate a system reset by driving this pin low for at least 15 μs[/B].
hi,
The way I read the above is that the pin can act as input for a system RESET.
Is like most I/O pins but without an internal pullup.

#### alphacat

##### New Member
Yes.

I dont think I managed to explain the problem.

1.Both RST pins of MCU and CP2102 are connected to each other and to pull-up resistor.
2. When I power up the system, the MCU experiences an HW reset.
3. When I remove the CP2102 from the PCB, and power up the system, the MCU doesnt experience an HW reset.

Do you see any reason for the CP2102 to cause an external reset to the MCU?

#### tkbits

##### Member
That's what it's supposed to do.

Table 5 shows that the RST pin is both an input and an output. The open drain allows this.

The CP2102 RST pin outputs a reset signal during power up, as it is driven by the internal Power On Reset (POR) signal.

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#### alphacat

##### New Member
Thank you.
Do you have a link to where open drain is explained, besides whats written on Wiki?

I'm not familiar with the term and its structure, so i'd like to learn about it.

#### ericgibbs

##### Well-Known Member
Thank you.
Do you have a link to where open drain is explained, besides whats written on Wiki?

I'm not familiar with the term and its structure, so i'd like to learn about it.
hi alpha,
Look at the section covering RA4.

PIC16F84A Detailed specification (2)

#### alphacat

##### New Member
Hey Eric.

It was very good.
An open drain pin is high impedance when VGS < VT.
To reach 0L output, the mosfet is brought to linear state or saturation state?
I'd appreciate it if you could explain why its in linear/saturation state in 0L state.

Lots of thanks as always

#### ericgibbs

##### Well-Known Member
Hey Eric.

It was very good.
An open drain pin is high impedance when VGS < VT.
To reach 0L output, the mosfet is brought to linear state or saturation state?
I'd appreciate it if you could explain why its in linear/saturation state in 0L state.

Lots of thanks as always
hi,
Can you confirm what you mean by OL, do you mean Output Low, if yes the mosfet is saturated.????

#### alphacat

##### New Member
Yeah I meant 0 logic.

What is the advantage of being saturated over linear state?
If I recall right, rds in saturation region is smaller than rds in linear region, is it becaues of that?

#### ericgibbs

##### Well-Known Member
Yeah I meant 0 logic.

What is the advantage of being saturated over linear state?
If I recall right, rds in saturation region is smaller than rds in linear region, is it becaues of that?
hi alpha.
May I ask, is this homework.?

The advantage is that in saturation the dissipation within the device should be at a minimum.

Rds is an inverse function of Vgs and Ids.

#### ericgibbs

##### Well-Known Member
hi,

Look at this graph, the datasheets for MOSFET's give lots of info.

EDIT: another type.

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#### alphacat

##### New Member
Hey Eric.

Its not homework, I start my third year in EE only in November 09.

What is the reason that the dissipation within the device in saturation is at minumum?
isnt it becuase rds in saturation is at minumum, and therefore for a given IDS current, the double I^2/rds will be at minumum?

#### ericgibbs

##### Well-Known Member
Hey Eric.

Its not homework, I start my third year in EE only in November 09.

What is the reason that the dissipation within the device in saturation is at minumum?
isnt it becuase rds in saturation is at minumum, and therefore for a given IDS current, the double I^2/rds will be at minumum?
hi,
Basically yes, look at the edit image in last post.

#### alphacat

##### New Member
Alright, I understood these pictures, I think, and my mistakes also.

In saturation region, rds is infinite, since the tunnel is pinched off, not allowing more electrons to pass in a certain time interval.
The current can still increase with increasing VDS, since the tunnel gets shorter.

Therefore in the graphs you see that there is a point where rds gets infinite, and this is the point where the MOSFET enters saturation region.

I hope I'm correct.

I cant thank you enough for your great patient you've shown.

Lots of thanks!!! next time you should explain to me what the movie Traffic is about, I didnt understand its purpose at all when saw it yesterday.

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