Obscure but Interesting Circuits 2014-04-01

Val Gretchev · Apr 1, 2014

Val Gretchev submitted a new article:

Obscure but Interesting Circuits - Having fun with logic gate circuits that may be useful.

I want to make you aware of a couple of interesting circuits I came across over the years. The file “LatchSync.JPG” shows a clip of the two circuits.
I found a simple logic simulator on the Internet at https://sourceforge.net/projects/cedarlogic/?source=dlp and used it to test the circuits described below. I you chose to download the free program and install it, you can load the design file “Latch and Sync Circuits.cdl”...

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RichTheDude · Apr 14, 2014

Nice collection of circuits, although latches are best avoided in FPGAs unless the designer is very careful. Asynchronous circuits are an easy way to introduce timing errors.

Val Gretchev · Feb 13, 2015

I used to enjoy making state machines with asynchronous latches. As long as the progression from state-to-state was in Gray Code (only one latch changing state at a time), you could avoid invalid conditions. Decoding of states was also easier and produced no glitches. The design involves use of Karnaugh maps for precise control of the design. I can see that FPGA design tools would have to be manipulated to get the same results in order to avoid timing errors.

Obscure but Interesting Circuits 2014-04-01

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Obscure but Interesting Circuits 2014-04-01

Val Gretchev

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