NMOS logic design

[PG1995]

Hi

Could you please help me with this query? You can see the complete chapter here. In the attachment I'm referring to the chapter's page number not that of PDF file's page number. Thank you.

PS: The author kind of elaborates on what he really means by "worst-case logic state situations" in second-to-last paragraph on page #325. Example #6.9 on page #331 is also useful where the author says "and transistor sizing will follow the worst-case path approach".

 

[dougy83]

Well, you've stated that Ron = L/W so all calculations are simply those used for resistors.

There are two current paths to ground from Y. One through A & B, and the other through C & D & B. The worst case resistance to ground is when only one of these current paths are conducting.

If both current paths are conducting, then the resistance to ground will be reduced and is obviously not worst case.

You simply have to find some values for L/W that allow the total resistance from Y to ground to be 1/2.22 (assuming as you wrote Ron = L/W).

Referring to the left diagram, if the path A&B is formed, the resistance from Y to ground is Rab = 1/3.33 + 1/6.66 = 0.45... the W/L value is 1/0.45 = 2.22, which is what was asked for.

If path C&D&B is formed, the W/L from Y to ground is 1/Rcdb = 1/(1/6.66 + 1/6.66 + 1/6.66) = 2.22, which is also the value you're after.

The same goes for the values in the figure to the right. 1/(1/4.44 + 1/4.44) = 2.22 = 1/(1/8.88 + 1/8.88 + 1/4.44) = 2.22

 

[PG1995]

Thank you, Doug.

There are two current paths to ground from Y. One through A & B, and the other through C & D & B. The worst case resistance to ground is when only one of these current paths are conducting.

If both current paths are conducting, then the resistance to ground will be reduced and is obviously not worst case.

I think in this example being discussed, the W/L ratios have been found keeping in mind the worst case scenario. The resistance of the path CDB is equivalent to the resistance of reference design; and same is true for the other path AB. Previously I had thought that combined resistance of all the transistors should be equal to that of the reference design.

You said, "If both current paths are conducting, then the resistance to ground will be reduced and is obviously not worst case." Why would it be worst case when only one path is conducting and the voltage increases? Could you please elaborate on it? Thanks.

Regards
PG

 

[dougy83]

Why would it be worst case when only one path is conducting and the voltage increases? Could you please elaborate on it? Thanks.

Because you want your output low voltage to be at most that of the reference design. If the voltage is less (due to the pull-down network resistance being decreased), then it's obviously better than worst-case. I think you may have missed the work "not" in my statement.

 

[PG1995]

Thank you.

I think you may have missed the work "not" in my statement.

No, I didn't miss it! Let me phrase my question differently. I understand when we have two resistances in parallel then the equivalent resistance is less than both. Let's say low voltage is 0.2V. Why would it be worst case if low voltage increases to 0.4V when only one path path is conducting? In my opinion noise margin can accommodate this little increase in voltage. Do you get me? Thanks for the help.

Regards
PG

 

[dougy83]

I didn't read the question in the attachment and just when on the answer. Isn't the goal to design a logic gate that has an output voltage no worse than the reference design? This means the output low voltage can be no higher than the reference output low voltage... ever!

 

[PG1995]

Isn't the goal to design a logic gate that has an output voltage no worse than the reference design?

I don't know but now I think that's the goal. The author didn't say explicitly that an output voltage should be no worse (or, higher) than the reference design but the end W/L ratios have been chosen in such a way that the voltage can drop below the reference design's low voltage but it never goes above the reference low voltage. Thanks.

Regards
PG