Friends,
Please see a portion of the codes that I have used in a project. Every thing is OK. But in a very rare case the processor behaves in improper way.If a condition of a bit test is fulfilled, the processor jumps to INV_ON where PORTA, 2 is set and then PORTC is cleared. Sometimes it is noticed that on jump of the processor to INV_ON, the first instruction to set PORTA, 2 is not carried out. But the next instructions from CLRF PORTC onwards is carried out. Is there any chance for the processor to slip over the first instruction after jumping to INV_ON? If so, could it be eliminated by using some NOPs before the first instruction?
Thanks.
swapan
Please see a portion of the codes that I have used in a project. Every thing is OK. But in a very rare case the processor behaves in improper way.If a condition of a bit test is fulfilled, the processor jumps to INV_ON where PORTA, 2 is set and then PORTC is cleared. Sometimes it is noticed that on jump of the processor to INV_ON, the first instruction to set PORTA, 2 is not carried out. But the next instructions from CLRF PORTC onwards is carried out. Is there any chance for the processor to slip over the first instruction after jumping to INV_ON? If so, could it be eliminated by using some NOPs before the first instruction?
Thanks.
swapan
Code:
INV_ON MOVLW B'00000100'
MOVWF PORTA
CLRF PORTC
BTFSC PORTA,3
GOTO $+2
GOTO $-2
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