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Need help with time delay relay

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99SH

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I've been looking at some time delay relay circuits using the 555 timer and it doesn't seem to do what I want. Here's the problem. I want a 2 second delay generated whenever a trigger(momentary switch) is detected. So whether the switch is held down for 5 seconds, or 10 ms(for example), I always want a 2 second high output.

Any help is greatly appreciated.

-Arax A.
 
Start with the monostable described in the 555 datasheet. For what you want to do, you need a differentiator, so that your trigger pulse is always shorter than your output pulse. Add a 10k resistor from pin 2 to +V, a 0.1uF capacitor from pin 2 to one terminal of a normally open switch, a 100k resistor to +V from the junction of the switch and the 0.1uF cap, and connect the other end of the switch to ground. If your trigger is a voltage (meaning you aren't using a switch), describe where it comes from and we'll go from there.
 
The trigger is actually a switch. The switch, which is user controlled, which may or may not always have a period which is shorter than the output pulse.
 
99SH said:
The trigger is actually a switch. The switch, which is user controlled, which may or may not always have a period which is shorter than the output pulse.
OK, then what I described will work.
 
OK, I tried what you said and it worked beautifully. Thanks alot for your help, it really did alot.

I have one more addition to this project, now that you solved my initial problem. How do I make it so that it'll only output the delay pulse only on the first initial trigger, and discard all other triggers?
 
It would have been simpler if you had said that in the first place. There are lots of ways to do this, but this is probably as good as any. I added a reset switch. You can eliminate the reset switch and have it work only once after each time the power is turned on. Here is the CD4011 datasheet.
 

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Could you explain to be why you have the 0.1uF capacitor, diode & resistor. The circuit seems to work fine with just the R/S latch network.
 
When the trigger switch is pushed, the latch output (the lower output of the cross-coupled NAND gates) goes low and stays low until reset. Pin 2 of the 555 has to go low to trigger it, but it has to go back high before the 555 times out. The capacitor and 10k resistor form a differentiator to assure that this happens - just like in the previous solution I described. The diode is protection against potential excessive current into pin 2 of the 555 when you reset the latch. You didn't need the diode in that circuit, because the 100k pullup resistor on the switch limited the current to microamps.
 
**broken link removed**

I really need to find a better way to post circuits, Ron H what do you use?

Anyhow from left to right C1 2uf, C2 1uf, R1 10k, R2 2M

When the input goes high it forces C2 to go high at the input of the gate, C2 will slowly discharge through R2 creating your 2 sec timer. To retrigger you have to remove the high from the circuit input and reapply it.

You can use a transistor but the current flow though the base will affect the cap discharge timing, this would best best done if you use a darlington pair and constant load.
 
99SH said:
OK, I tried what you said and it worked beautifully. Thanks alot for your help, it really did alot.

I have one more addition to this project, now that you solved my initial problem. How do I make it so that it'll only output the delay pulse only on the first initial trigger, and discard all other triggers?

Opps just noticed this bit.
{edit} I posted an add on to the circuit so it latches but it was a little confusing so I decided to post the whole thing.

**broken link removed**
 
Dingo, I draw my schematics with Linear Technology's SwitcherCAD III, which is a totally free Spice simulator. I then use a freeware screen capture program to save the schematic as a .GIF file.

Regarding your circuit - it is definitely simpler than the one I suggested. I do have a critique, which I inflict on many posters. Feel free to reciprocate.

99SH wants the output to be a positive pulse, so you need to add an inverter, which is not a problem, since you have at least 3 left over.

What is the purpose of the 1uF capacitor? I think this will guarantee an output pulse every time power is applied - probably not desirable feature.

Are you sure the latch will come up in the untriggered state every time you turn on the power? Speaking of that, my latch has this problem. I have edited it to add this feature.

Your LED is backwards, and needs to be connected to +V.

One of the big features of the 555 timer is that its timing is easily calculated, is repeatable from unit to unit, and is virtually independent of supply voltage. I suspect this is not true of your circuit. This may not matter if this is a one-off project.
 
Ron H said:
Dingo, I draw my schematics with Linear Technology's SwitcherCAD III, which is a totally free Spice simulator. I then use a freeware screen capture program to save the schematic as a .GIF file.
There is an in-built function in SwitcherCad to copy schematic to Clipboard in Bitmap format. You can paste it to MS-Paint and then save it as GIF. You'll find this function in "Tools" menu.
You may find this easier than taking screen shot.
 
Thanks Ron H that program looks good is there more libraries I can load into it?

The circuit above, yup LED is the wrong way around, and the circuit most likely will power up in alarm mode although I'll refer to it is as "power up test mode" :D

The 1uf is critical as it is what does the timing, the 2uf is there to charge up the 1uf, this means that no mater what your input duration you get the same timing. 1uf with 2m resistor this will give about 2 sec, change it to 5m should give 5 sec.

You are correct about the 555 but I haven’t used one in years, with simple timing I use caps or binary ripple counters. Nice thing about ripple counters is you get about 10 different clock speeds in one go. Need accuracy then I throw in an xtal.



**broken link removed**
 
OK, I want to make sure I understand this correctly. Looking at the first schematic:

When the circuit is powered up C1 is not charged up(as it has V+ on both leads), and pin 2 of LM555 is at a logic high. On trigger event, C1 initially acts as a short which puts Pin2 to a logic low. But then C1 starts charging up through R3, and when it reaches full charge turns Pin2 to a logic high.

Do I have this correct?
 
99SH said:
OK, I want to make sure I understand this correctly. Looking at the first schematic:

When the circuit is powered up C1 is not charged up(as it has V+ on both leads), and pin 2 of LM555 is at a logic high. On trigger event, C1 initially acts as a short which puts Pin2 to a logic low. But then C1 starts charging up through R3, and when it reaches full charge turns Pin2 to a logic high.

Do I have this correct?
Basically. The threshold voltage of pin 2 is VCC/3. When pin 2 drops below VCC/3 (which, in this circuit, is when the trigger switch is pushed), it sets an internal latch which starts the timing cycle. Pin 2 must be above VCC/3 before the timing cycle ends, which is when pin 6 crosses its threshold of (2/3)*VCC and resets the latch. This is the reason for C1 and R3.
The output (pin 3) is high while the latch is set, and low while it is reset.
 
Dingo said:
The 1uf is critical as it is what does the timing, the 2uf is there to charge up the 1uf, this means that no mater what your input duration you get the same timing. 1uf with 2m resistor this will give about 2 sec, change it to 5m should give 5 sec.
You don't need the 1uF cap. you can get the same results (minus the power up test mode) with a single 1.5uF cap.
 
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