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Need advice on the following implementation

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pavjayt

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Not sure how to write the subject line for the following question. Basically the project is to derive certain signals/waveforms from a given master signal. Currently this is all hardware based and would like to move it to a user programmable interface and probably using a microcontroller (maybe a basic FPGA). This is totally new to me and hence need some good advice based upon your experiences.

Input - is a master clock anywhere between 15Khz - 16Khz, this is a pretty stable signal and is available either in sine wave form or TTL form
Output 1 - a pulse train based on input (this can be a fixed width, doesnt need to be programmable)
2 - a pulse for every X number of input clocks (again this can be a fixed width, but needs to be user programmable for X, where X is usally >512)
3 - a ramp signal with the frequency of output 2 (needs to be user programmable for offset & amplitude & low to high or high to low option)

Need a programmable delay for input signal. Then the input should be fed into a PLL that can be used down the stream for generating outputs 1-3. User should be able to control the above from a PC (any kind of interface works).

Any ideas/suggestions?

thanks in advance
 
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Schmitt trig gate/inverter to square up the input clock?
12 or more bit binary presetable up-counter driving a DtoA?
Set the amplitude and direction (inversion) of the ramp using an opamp(s)?
 
Schmitt trig gate/inverter to square up the input clock?
12 or more bit binary presetable up-counter driving a DtoA?
Set the amplitude and direction (inversion) of the ramp using an opamp(s)?
Thanks for your suggestions, but I already have everything done by pure hardware (74HC ICs, 556 timers, 12bit counters etc). I want to do the same using an FPGA to program and control the above and have a PC interface. Not sure where to start for this other than reading books on FPGA.
 
Seems straightforward for a micro. They're good at counting, detecting user input from keypads etc, and outputting a PWM signal which can be smoothed to give a ramp with offset and programmable amplitude. An opamp can then give polarity selection.
 
FPGAs dont do D/A, nor the analog parts, so the best you can do is to build a presetable counter inside the FPGA
 
FPGAs dont do D/A
You could, however, use weighting resistors on a set of FPGA outputs to get a simple D/A.
 
Simple D/As consisting of resistors connected to digital I/O pins are good for maybe 4 to 6bits; OP needs 12.
 
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