MOSFET use

[malc9141]

Hi

With an n-MOSFET (IRF630), can I control the current flow by varying the Gate voltage? Or does it act only like a switch (unlike a BPT) ?

Reading, I get the impression that the current flow is just V/R of rail circuit and can't be factored usefully by varying Gate potential.

Malc

 

[crutschow]

You can vary the drain-source current by varying the gate-source voltage but for stable control you need to use negative feedback (such as a adding a source resistor). That's a common way to make a constant-current source, for example.

 

[malc9141]

Thanks muchly. Let me say, largely understanding the principal of the FET, I thought it should be able to act as a current controller. (The voltage, ie a force, applied to the Gate causes electron movement, a la static electricity). So, I reasoned, between zero and high voltage applied, the internal "resistance" should decrease. Therefore, it could be used as a controller like a BJT (recognising that it's Base current for a BJT).

In fact, the MOSFET does work as I suggest, and you say - if I get you right - but its so marginal as to be useless. I took my IRF630 and using a LED and a variable resistor, I found it was essentially ON-OFF. But the D-S voltage did change with the applied G voltage - through a small range of about 2 v against a 12 v background. Not helpful for my circuit.

For my needs, therefore, I used two MOSFETs in parallel, each with its own R, so I could switch between them to get the two different currents I wanted.

 

[audioguru]

The maximum allowed gate-source voltage for most Mosfets is only 20V. Any more voltage will destroy the gate. Static electricity is 20,000V or more.
The datasheet for an IRF630 Mosfet shows that some of them barely turn on (conduct a very low current of only 0.25mA) when their gate-source voltage is 4V but all of them conduct at least 5A when their gate-source voltage is 10V.

You should use two power resistors in series with the load to select the load current. A switch selects which resistor and the output of one Mosfet drives the input of the switch.

 

[kubeek]

Basically it is possible, but usually you would use a mosfet together with an opamp feedback to create a quite stable current source.

 

[malc9141]

Just on the static point, obviously it is usually used talking about a high voltage but it could be anything. I accept its an odd way of me to use the term. But I do think the Potential on the Gate is associated with a "field" which interacts at a distance (photons) with the electrons on the sides, causing them to move and reduce resistance in the semiconducting material. This is how I see it. I could be wrong.

The Gate gets ~5.5 v. The main line is 15 v, with a brief 5 A current, then a 2.5 A current.

I have done much as you say: I have the timed input (0.7ms) to both FETs and the longer pulse (~2 ms) to one only. Each has its big R on the Drain side. The Drains join up. The load (a coil) is on the Source side. A diode rather than a zener connects ground to Drain.

Seem OK to you?

Thanks

Malc

 

[audioguru]

Seem OK to you?

Without seeing your schematic then I do not have a clue about what your circuit is doing.

 

[malc9141]

The schematic is imperfect so I'll leave it just now.
But can you help with one thing? Using the ic4093, we have Pins 2 thru 13, four separate Flip-flops. Pin 14 is +6 v, Pin 7 O v.

As a circuit is closed intermittently to ground, the voltage coming in to the 4093 falls off.

I therefore am putting a varied (Logic 0) signal in to Pin 2, with + 6 v at Pin 1. I get a square wave + signal at Pin 3 (Logic 1).
I feed this (via a cap & resistor to fix its duration) into Pin 5, with Pin 6 at O v (ground).

As I understand the Data sheet and Truth Table, I should get a timed square wave out at Pin 4.
I am told this is not so. "The gate won't work".

Please confirm/refute.

Malc

 

[kubeek]

The schematic is imperfect so I'll leave it just now.
But can you help with one thing? Using the ic4093, we have Pins 2 thru 13, four separate Flip-flops. Pin 14 is +6 v, Pin 7 O v.

As a circuit is closed intermittently to ground, the voltage coming in to the 4093 falls off.

I therefore am putting a varied (Logic 0) signal in to Pin 2, with + 6 v at Pin 1. I get a square wave + signal at Pin 3 (Logic 1).
I feed this (via a cap & resistor to fix its duration) into Pin 5, with Pin 6 at O v (ground).

As I understand the Data sheet and Truth Table, I should get a timed square wave out at Pin 4.
I am told this is not so. "The gate won't work".

Please confirm/refute.

Malc

This is absolutely meaningless without a schematic. What does "as a circuit is closed intermittently to ground" even mean? You say somethng about four flip flops without any connections whatsoever, but then you start talking about circuit being closed...
I dont have a crystal ball to see what you got inside your head or on your table.

 

[audioguru]

A CD4093 IC has four 2-input NAND gates with Schmitt-trigger inputs, it does not have any flip flops. If either or both inputs of a gate are low then the output will be high. If both inputs are high then the output will be low.

You said you have a "varied" (Logic 0) signal into pin 1 but logic 0 is 0VDC, not a signal. Maybe you have a random signal that goes high and low?
Since pin 1 input probably has a high and low signal and since you have pin 2 input high then the output pin 3 has a rectangular wave but why do you say it is Logic 1 which is a DC voltage?

I guess you use a capacitor to couple the pin 3 output into the pin 5 input that has a resistor to ground but you should not use a capacitor to couple a logic signal, because the input protection diode prevents AC below ground voltage swings.
What duration do you want to fix??

 

[malc9141]

broken link removed Here is the part of the circuit in question. (Of course, it doesn't upload. Why not?)
As you can tell, I am not an electronic engineer (I'm having to act as if !).

I get told to "look at the Data Sheet" (1c4093) and the Truth Table. This is what I suggest, in order to get a positive square wave output of specific time (RC x ln V-v /V @ 25 deg C etc) from Pin 4.

The table suggests that if 5 and 6 are opposite, 4 will be positive.
***************************************************************************************
The ic4093 is set with +5v at pin 14, O v at pin 7.

Below, please imagine B gets a dropped voltage from 5 v to zero, as a sensor (to the left of A) closes a circuit to ground. A is fixed at 5 v. Then, there should be a + ve signal from Q1 (pin 3).


Now, below, this is the second gate (if thats the right word). I'm sorry I am stuck with A and B again, but please imagine its the independent second gate in the 4093.
Q1 (pin 3 on the ic 4093) goes to second B, below, via a 15 nf cap, then thru 47K R to O v.
The second B, pin6 goes to O v. So pin 4, the second Q2 should be a timed + pulse.


Is this correct? Thanks in advance.
Malc

 

[audioguru]

The first time the B input of the first gate goes to ground and its output goes high will allow the 15nF capacitor to pass a positive pulse to the B input of the second gate which has a resistor to ground. If the A input of the second gate is high then the capacitor at the B input causes a logic high for a certain duration then as the capacitor charged by the resistor it causes the the B input to go low.

But the gate inverts. When both inputs are high then the output is low. The timed pulse at the output of the second gate will go to ground, it will not be a positive pulse.

When the capacitor is charged and the output of the first gate resets to be low then the charge on the capacitor causes the input of the second gate to try to go to a negative voltage which is not allowed. The gates might be destroyed.

Since you need a timed pulse then why don't you use an LM555 timer IC to produce the pulse? Its input goes low to start the timed positive output pulse. A low supply current Cmos 555 is available as a TLC555, LMC555 and ICM7555.

 

[Mosaic]

Regarding the OP's FET concerns.
MOSFETS operate based on a voltage on the gate to control current thru the source/drain to its maximum rated values. They are transconductance devices.
Bipolar transistors operate based on a current thru the base to control a current flow thru the emitter /collector. Thus MOSFETS consume notably less current (no base drive) than bipolar in higher current applications.

They both permit current control/switching and current amplification. You can achieve control by passing this current thru a resistive load and using that as feedback. A current can be manifested as a voltage on a MOSFET gate via resistor biasing.
For signal amplification, keeping the devices in their linear range (gate voltage/base current) is important for signal integrity.

This is more detailed:
http://blog.oscarliang.net/bjt-vs-mosfet/

Also, to truly understand FET small signal biasing etc:
https://www.electro-tech-online.com/threads/video-lectures-circuits-and-electronics-6-002.119523/

 

[malc9141]

Thanks so much. (Funnily I have a 555 to artificially create a timer to test the circuit).

First (as is obvious, I'm not an electronics engineer - I'm a mech eng). I have been using successfully a complicated circuit we built about 8 years ago, when there was scant available data publicly available for a Common Rail diesel injector - these run extremely fast by operating at >>1000 atm pressure. Allowing very precise fuel delivery.
The guy who designed and built this has kept saying it could be simplified, now that we know what we know, but has never built it for us. There now are rather crude items (eg LM1949) available, and better ones which are, however, with tiny pins and masses of redundant complexity.

It seemed we could build a simple circuit which put a 0.7 ms FIRE pulse through the circuit at 5 A, followed by a variable (1 - 3 ms) HOLD pulse at 2.5 A, using two MOSFETs in parallel. I got helpful advice and nearly built it, and was putting the FIRE and HOLD times into either side of a ic4013.

But going back to the 4093, I suggested (as a query) putting the signal (O v) into Gate1/pin2, and thence to Gate2/pin5, and then output to Gate3. Then I was told that was too complicated so I suggested the plan above. Obviously, its no good but I don't want to add a 555 if I can use more of the 4093 gates. I know we're "nearly there". I do not enjoy, too much, this building stuff because someone else promises but doesn't act. And starting over in yet another's hands is a risk I don't want to take (because s/he won't exactly know what I need, as I have found).

I'll ponder on this very exact reply of yours. Thanx once more -

 

[malc9141]

MOSAIC

Thank you!
Will look.

More surprised at the "easy" 4093!!

 

[Mosaic]

So you're overcoming injector inertia with the 5A pulse and then maintaining the injector open with a 2.5A variable pulse. Presumably the 2.5A doesn't saturate the injector coil and cause heating. Also you must consider inductive kickback snubbing.
How do you vary the 1-3ms pulse fueling phase?
Perhaps this might interest you.
https://www.diyautotune.com/diypnp/

 

[malc9141]

Thanx MOSAIC (I know all about the inj ! The snubbers in). The 2.5 A pulse: you give two of the reasons; the most important tho' is that we need to CLOSE the cycle "instantly". This is easier with less power in the tiny (0.15 mH) coil.
Incidentally, I did various calculations about the kick-back V before knowing all about the inj. I was imagining 500 V or something. It turned out to be ~6 V when we measured it!


https://malcolmcochran.wordpress.com/2013/12/10/electronic-circuit-for-delphi-injector/

 

[malc9141]

This is the scheme. But the main area was the 4093.
Pins 1, 6, 9, 14 get + 6 v. Pin 7 -> O v.
Pin 4 feeds Pin 8
Pin 10 is the + output.
Thank you for clarifying. If other FAULTS are seen, let me know.

Mosaic, the second set of RC with the potentiometer is the "accelerator". One of the caps can be changed. It works fine.

Malc

 

[Mosaic]

With a 6V Vgs and a 220 Ohm Gate resistor the on/off switching of the device is not optimized. Of course this reduces the kickback event as well at the cost of some heating in the FETs. I see a 22K resistor in the voltage regulator. This seems large. It implies that to maintain at most a 7 volt drop to keep the 7806 regulator supplied @ 8V or better the max current draw is (7-0.6)/22000 = 0.28mA. The 100nf decoupling cap near the 7806 Vreg is placed where? Hopefully as near to the 4013 logic chip's pwr terminals as possible.

A quick calc
The 220 ohm Rg => (Vg-Vth)/Rg= (6-4)/220 = 9 mA max Ig. But looking at the 4013 spec sheet, to maintain the Vth of the IRF630 of 4V the 4013 (Vcc=6V) would be sourcing about 3mA max. Given the .28mA supply, the 100uF and the 100nF should be able to maintain a 3mA 'spike' for the switch on cycle, which is < 10% Duty. More than 10% duty will cause the switching time on the FETs to be impacted....
The total gate charge on the IRF630 is 35nC thus the switching time is then 35 nC/ 3mA = 11.7uSec.
A 700uSec fire pulse will then actually occur 11.7 uSec later than the pulse, plus you must consider the inertia of the injector and its response specifications. If the inductance of the connection to the Gate is significant it could add a couple more uSec to the delay.

Since you have a Peak-Hold type of injector supply, it implies that you are using low impedance, hi performance injectors for tunability. The delays introduced by the MOSFET switching will reduce your tunability. Whether that is significant is up to you.

 

[malc9141]

I see a 22K resistor in the voltage regulator. This seems large
Well spotted. Its a 1K R in the voltage control. My wrong drawing. Is 1 K suitable? Please rework your "quick calcn" if you think it needs it.

6V Vgs and a 220 Ohm Gate resistor
I don't see the point of this but copied it off a commercial circuit. I think it was to reduce heating (but I thought the FETs wouldn't heat when they are only active for, say, 3 ms, in a 25 ms cycle ( 25 ms = time per rev at 2400 rpm)).

The 100nf decoupling cap near the 7806 Vreg is placed where? Hopefully as near to the 4013 logic chip's pwr terminals as possible.
Well, its right beside it though not actually on the "legs" of the TO-220. Your comment seems very smart! I also don't know why I have the Tantalum cap: all this is copied off the original complex circuit which was designed by an expert.

A 700 uSec fire pulse will then actually occur 11.7 uSec later than the pulse, plus you must consider the inertia of the injector and its response specifications. If the inductance of the connection to the Gate is significant it could add a couple more uSec to the delay.
Since you have a Peak-Hold type of injector supply, it implies that you are using low impedance, hi performance injectors for tunability. The delays introduced by the MOSFET switching will reduce your tunability. Whether that is significant is up to you.

I value this bit, too. But we are OK with that 1.5% delay. At first, not knowing the inj's characteristics, we sweated over this but it is all OK. In the inj, low-mass parts are moved small distances with large forces (1500 bar is about 5 tons/sq in or something).

Can you look at the RC circuits, please, with regard to their timing? There are 2. One for the initial sq wave, which is also Fire; another for the Hold. In particular, is the common wire from that timer, through the Hold FET with the voltage divider, OK? (I copied that V divider from a professional circuit with that FET).

Malc