Missing Pulse Detector with Varying Input Frequency

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There's many solutions that would work, the PLL, analogue voltage, microcontroller.

But it's the initial problem that's flawed. If you are restricted to 1 wire, just use a better system for making the reset. Ie just a different voltage (or polarity) reset pulse.

Mess with the problem first, then the solution gets easy.
 
Thanks, I think that is the perfect solution. Sometimes the answer is staring you in the face but you just can't seem to see it.

I'm not good with analog (more of a software/digital guy), but I know there's a circuit that can generate a specific width pulse on the leading edge of a pulse. This would convert my 50% square wave into a train of pulses of equal width no matter the frequency.

Anyone know what that circuit is called and how to make one?
 
I don't know of a specific type of circuit that will do this. I have a prototype analog circuit to generate a 50% duty cycle from a signal of arbitrary frequency, but it's complicated. One solution is to use a simple flip-flop. The resultant signal will be 1/2 the frequency of the input, but if you're only using it to detect a missing pulse, you might be able to make it work.
 

That's not needed!

Your train of clock pulses just clocks the receiver device on the leading edge of the pulse. It's rare for any digital device receiving clock pulses to clock on BOTH edges of the pulses!
 
Anyone know what that circuit is called and how to make one?

It's called an edge detector. You can just use a series capacitor followed by a shunting resistor to ground; but for a cleaner signal, this should be followed by a schmitt trigger.

Likewise, the receiving end is a resistor followed by a capacitor to separate the reset pulses out from the clock. The schmitt trigger is optional, but may improve the function.

Have a look at the attached schems. The component values may be wrong, they they should be a start.

If you don't use buffering (e.g. the schmitt trigger) on the sending circuit, you'll have to more careful with the receiving end - the cap in the sender should be >> than the cap at the receiver.
 

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After reading Dougy83's post, I realized I mis-understood the question. In fact, the whole thread makes my head spin. Please disregard my previous post.
 
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