That's a pretty poor data sheet that doesn't tell you how to use it. Try this:
The AC273 and ACT273 have eight edge-triggered D-type
flip-flops with individual D-type inputs and Q outputs. The
common buffered Clock (CP) and Master Reset (MR) input
load and reset (clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each Dtype
input, one setup time before the LOW-to-HIGH clock
transition, is transferred to the corresponding flip-flop’s Q
output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The
device is useful for applications where the true output only
is required and the Clock and Master Reset are common to
all storage elements.
The gist of it is:
There logic levels at the eight D inputs get sent to, and latched at, the Q outputs when the CP pin (the clock input, might be named differently on your sheet) rises from low to high. When the MR (or RST or RESET) pin goes low it forces all the Q outputs low at the same time, regardless of what the clock is doing.
So, in most situations, at the start, the MR pin is made low so all the outputs start at a known level. The clock is either constant high or low. Things remain this way until the clock switches from a low to a high. This is a "rising" edge. This edge makes the output latch the levels at the inputs. These input signals need to be stable a certain amount of (very short) time before and during this latching action. These are called the "setup times", which are given in the data sheet.
These things get used all over the place.
You can drive the inputs on a 7-segment LED display by latching 8 bits of data out of a processor. Using another '273, you can take the same 8 bit port on the same processor and drive another 7-segment display without interfering with the first display. You simply dedicate a few other pins to drive the clock inputs to each individual Flip-Flop. You could use six (more or less) displays by supplying each with its own '273 and six pins to clock and latch the data one '273 at a time.
Hope that helped.
kenjj
BTW, the ACT in 74ACT mean:
A for advanced (faster, less power used)
C for CMOS construction, so uses less power by design
T for TTL levels, so considers a LOW level to be less than 0.8V, while a HIGH is greater than 2V (typically)