Is there code in your circuit
Not in the circuit I posted. Hardware logic provides the A and B relay drive signals.
By way of explanation of the circuit, gates U2a and U2b together act as a monostable circuit with a period of about 40mS for 'debouncing' the gear-switching signal from the 'up' switch contact or the 'down' switch contact. The switch can be a single-lever single pole momentary type with a centre-off position (i.e. mom-off-mom).
After the 40mS delay the BCD counter U1 is clocked by the rising edge of the pulse from the monostable. Whether the count is up or down is determined by the state of a set-reset latch formed by gates U5b, U5c.
The count value at outputs Q1, Q2 is monitored by gates U3a, U5d. Gate U3a detects a count of '0' and sets the latch, which enables up-counting by U1, enables (via gate U5a) the 'up' switch to clock the counter, and blocks (via gate U2d) the 'down' switch action. Gate U5d detects a count of '3' and resets the latch, which prevents further up-counting, switches the counter mode to down-counting, enables the 'down' switch action and blocks the 'up' switch action.
The counter outputs control the multiplexer U4 such that a count of '0' (= 1st gear) connects I0a to Ya and I0b to Yb, thus putting +5V on Ya and on Yb, signifying both relays 'on'. Similarly, count values '1' etc put other appropriate outputs (+5V or 0V) on Ya and Yb as per your table.
C2, R4 provide a power-on-reset function to ensure the counter starts at zero (1st gear). That may or may not suit your needs.
If you decide at a later stage that you wish the counter to count from 0 to 4 (or more) instead of from 0 to 3, the count monitoring logic can be changed and another multiplexer added.