LTSpice gotcha

[alec_t]

I'm a relative newbie to LTSpice and have been simulating a circuit using multiple data-latches of the 4013 type. Frustratingly, I couldn't get it to do what I wanted, so I tried a simpler simulation with just one latch to try and spot the error.
The relevant latch model that LTSpice offers is the 'dflop'.
I grounded the dflop D input and clocked the clock pin, expecting to see the Q output at 0. But no, Q = 1. Eh? What's going on? After much gnashing of teeth I discovered that by connecting the D input to a 0V voltage-generator instead of to ground, the dflop behaved as expected and gave me Q = 0.
I recall reading in the 'Help' for gate elements that LTSpice makes a distinction (for reasons best known to itself) between 0V and ground in connection with some inputs, but I couldn't see any reference to this in relation to the dflop. Indeed, I couldn't find any help at all for the dflop element!
A real 'gotcha' for newbies.

 

[ericgibbs]

hi alec,

The LTS 'Ground' isn't really Ground or 0V, its the reference node on the circuit, that LTS uses to calculate the plots

 

[crutschow]

Do you have the 0V node connected to ground? If not that would explain the problem.

 

[alec_t]

Thanks, guys.
Carl, I had the problem with a GND symbol attached to the 0V node and to the 'D' input of the dflop. Whether or not the bottom left corner pin of the dflop was connected to GND made no difference. Substituting a voltage generator set to zero for GND at D cured the problem!

 

[alec_t]

It gets weirder :-
(1) Connect D directly to GND, clock the dflop, get Q=1 [unexpected, as already described]
(2) Connect D to GND via a resistor (any value it seems, but I only tried 0.0001R and 1meg), clock the dflop, get Q=0 [expected]

 

[ericgibbs]

It gets weirder :-
(1) Connect D directly to GND, clock the dflop, get Q=1 [unexpected, as already described]
(2) Connect D to GND via a resistor (any value it seems, but I only tried 0.0001R and 1meg), clock the dflop, get Q=0 [expected]

hi alec,
Try this,, connect a short piece of 'wire' from the 'D' pin and connect the other of end the wire to Gnd.... lets know.

 

[alec_t]

Try this,, connect a short piece of 'wire' from the 'D' pin and connect the other of end the wire to Gnd.... lets know.

That was precisely the setup I had for case 1 above (sorry if 'directly to GND' was misleading).
I'll post an asc file of the various things I tried.

 

[alec_t]

Here's the asc file :-

 

[crutschow]

I ran the simulation and got the same results as you. Does appear to be a bug in the model.

 

[ericgibbs]

hi Alec,
Confirmed that model is suspect, I would recommend that you use the digital IC libs in future.
Modified asc attached.

 

[alec_t]

Thanks guys. Nice to know I've not lost the plot entirely!

use the digital IC libs

Do you know of any legit way of downloading CD4000.lib without joining the Yahoo user group? (I'm not a fan of Yahoo!!).

 

[ericgibbs]

Thanks guys. Nice to know I've not lost the plot entirely!

Do you know of any legit way of downloading CD4000.lib without joining the Yahoo user group? (I'm not a fan of Yahoo!!).

I dont know another legit way.
Why not bite the bullet and sign up with the yahoo user group, your design life will be much easier...

 

[Jony130]

Here you have 4000 lib
**broken link removed**

 

[alec_t]

Thanks, guys. CD4000.lib now installed.

 

[ericgibbs]

Thanks, guys. CD4000.lib now installed.

hi alec,
Libs for HC, HCT and HEF are also available.

 

[alec_t]

Thanks Eric, I'll look into that.
Another oddity (to me anyway): when I placed the CD4000.lib file in the 'lib' folder (which seemed the logical thing to do) LTS couldn't find it! So I moved it into the 'sub' folder and that's OK.

BTW, I emailed LT about the dflop model and got this reply from their Mike Engelhardt :-

"Grounding an input doesn't not mean logic 0, it means the pin doesn't
exist. The simulator then tries to do something meaningful. For example,
if you ground the input of an AND gate, it does not become a NOT
gate. Sometimes it's useful to have a D-flop with the input tied permanently
high but it would be nice not to have that node in the simulation out of
concern for the speed of the simulation.
The A-devices are to allow expert users to make macromodels that
run very fast, not teach digital logic. "

From that last sentence I think Mike was having a dig at hobbyists like me!

In response to my query as to how one should connect an input to represent logic 0 I was told "with a resistor".
So now we have the 'official' version.