Logic symbol question

[throbscottle]

I was looking at a data sheet today, and discovered that a nand gate is sometimes shown as an or gate with inverting inputs. A quick google told me it is a way for designers to show the implementation rather than just the function.

So can someone explain this to me please? Why would a gate be implemented in this way rather than in the standard way? And why would I want to know about it? After all, it's at a design level completely closed to me.

TIA

 

[MikeMl]

Not(A AND B) = Not(A) OR Not(B)

 

[throbscottle]

Thanks MikeMl, but I understand the logic, and that's not what I intended to ask. What I don't understand is the need to indicate the implementation.

Cheers

 

[JimB]

As Mike has said, a NAND gate can also be thought of as a negative input OR gate.

For example, the good old TTL 7400 is defined in the average datasheet as a Quad 2 input NAND gate.
However in some equipment schematics you will find that some sections of the 7400 are drawn as a negative input OR gate to reflect the logical operation of the circuit.
ie at that point in the circuit, either one of the two inputs in the LOW state will result in a HIGH at the output.

I first came across this concept many years ago when learning the inner workings of the PDP11 series of mini-computers.
Up until that point I had always seen logic gates drawn to reflect their stated function, rather than the circuit function.
I vaguely remember this notation being referred to as "Mill Spec Logic". I am prepared to be corrected on this statement if necessary.

JimB

 

[JimB]

gvtheogioH said:

Cam on nhhung chia se thu vi nay
Chuc ngay cuoi tuan vui ve va hanh phuc nhe

Google translate said:

Thanks for sharing this interesting
Happy weekend and be happy

JimB said:
Why do you feel it necessary to keep making trivial comments in a language which few poeople here will understand?
I can only think that you are of the ipod/pad/twitterbook/face generation who just have to issue forth with some verbal inanity at every possible moment.
Please stop.

Rightly or wrongly this is site is declared to be "English language only" by its owner.
So, adios, au revoir, auf weidersehen, ciao.
I will see you later to discuss electronics, in English.

JimB


JimB

 

[Mike odom]

ie at that point in the circuit, either one of the two inputs in the LOW state will result in a HIGH at the output.


I vaguely remember this notation being referred to as "Mill Spec Logic". I am prepared to be corrected on this statement if necessary.

JimB

the first part is 'spot on'.... sometimes it's easier to follow the logic flow by using inverted input OR gates, again, looking for one zero in to give you a one out. It's drawn to see what logic level the function is looking for to yield what output. The output decoder of our fire control computers on the sub were looking for 4 unique zeros (on the 24 bit word) to enable the ouput port.

Milspec logic is basically logic gates that are rated for the full -25 to +125°C operation. Generally they lead with an M (MD8085) from some manufacturers, and a different prefix for others, ex. National Semi linear components.... LM324 is commercial spec 0 to 70°C, LM224 is industrial spec 0 to 85°C, and LM124 is mil spec -25 to +125 (or sometimes +85)°C. You would assume the mil spec parts are better, but they are not. The specs for them are wider because they have to work over a wider temperature range, but they are guaranteed to work within those specs over that range. That's not saying an LM324 won't, but it's not guaranteed to, so some might and some might not.

Also, when we put LANs on submarines in the mid 80's, we built the interface between the network and the CIP panel (course indicator panel, what they look at to drive the sub) for the new Trident Missile Subs. Our LAN board was 16 bit and used an MD8086-2 (higher speed and mil spec version of the 8086), and we paid about $160 each for them, when commercial 8086's were going for around $25. I spent three days in drafting redrawing all the schematics to the LAN interface board, some 120 chips, because when we built the prototypes, we used ANDs and ORs. Well, a mil spec NAND gate cost about $5, and a mil spec AND gate cost about $20... so it was worth it for us to convert the ANDs and ORs to inverted input NORs (ANDs) and inverted input NANDs (ORs).

Some chips weren't available in mil spec, so we had to have them tested (and dotted) at the full temperature spectrum, complete with traceable paper work. I don't know if you recall TI got into trouble in the 80's for 'gundecking' (a Navy term for cheating) on their testing and control paperwork on their mil spec parts.

 

[JimB]

Mike

I am aware of "Mil Spec" in relation to the quality aspect of various components, and thank you for your insight into submarines.

It is just that I have stuck in my mind the expression "Mil Spec" in relation to these logic symbols.
It could be that my memory has become corrupted in the 30+ years since I heard the expression (and have not heard it used since).

Just took a break to do some googling and look what I found:
https://www.electro-tech-online.com/custompdfs/2012/11/BDE0054-04_catalog.pdf

It looks like the memory was not too far off after all!
Get the behind me Altzheimer!

JimB

 

[throbscottle]

Fascinating. I will have to look at the datasheet again (see page 7 of attachment). I feel like I need to do some kind of perceptual trick on myself here. "Mil" I take to be short for "military".

Thanks

 

[MrAl]

Hi,

JimB has explained this pretty well already, i'd just like to add a little here...

The 'new' symbol you have been seeing is negative logic, which you are used to seeing positive logic up until now.
So when you see a NAND gate you think perhaps:
"If both inputs go high then the output goes low"

and that is entirely correct, however there is an alternate conceptual view we can use due to the fact that there are only certain allowable states. That second view is simply:
"If either input goes low, then the output goes high".

Now compare the two quoted statements above. One is using 'high' inputs to explain the output result, while the other is using 'low' inputs to explain the same thing. So we say one is positive logic and the other is negative logic. They both ultimately say the same thing, but the conceptual view behind each way is a little different and this is illustrated in a simple example application...

Say we have a power supply, where we have two outputs one +5v and the other +10v. We have the over current mode set up to test either output to see if either has gone over 1 amp. So we can get 5v at 1 amp and 10v at 1 amp no problem, but if we go over 1 amp on EITHER output we want to turn the whole power supply off completely so nothing hooked up to it blows out. The logic statement for this action isnt too difficult, if we call the over current limit on the 5v supply A5 and the current limit on the 10v supply A10, and we shut down when the output of our logic gate goes low, we have a simple logic statement:
Out=NOT(A5 OR A10)
This tells us that Out goes low whenever either A5 or A10 goes high (either goes into over current mode), and we use that low to turn off the power supply.
So we can say,
"If either output goes into over current mode, Out goes low which turns off the power supply"

or we can also say,
"If both outputs do not go into over current mode, then Out goes high which keeps the power supply turned on".

So one way we are specifying what happens if either one goes into over current mode and the other way we are specifying what happens if neither goes into over current mode. But if you look at this as a whole, you'll see that they both really say the same thing because if you say it one way you have necessarily implied the other statement as well. This happens because of the limitation of possible states that stems from the fact that if you have a 1 then you cant have a 0, and if you have a 0 then you cant have a 1 (ie binary). As obvious as that sounds, it's one of the amazing things about binary: the limitation of states in a system leads to gross simplifications.

Our logic statement read:
Out=NOT(A5 OR A10)

or written slightly differently:
NOT(Out)=A5 OR A10 [ie either one high causes a low output]

so we have necessarily implied also this is true:
Out=NOT(A5) AND NOT(A10) [ie both low causes a high output]

 

[CmdrRickHunter]

I'll put forth a theory that hasn't been seen yet: the cheapest way to build a NOT gate, in terms of area, might be a NOR gate. If you got into very high speed signalling, this may affect how you approach the gate (as it stops behaving digitally and starts behaving like an analog device)

 

[throbscottle]

As always, MrAl, the depth of your knowledge astounds me!

Thanks

 

[dougy83]

They are called De Morgan's theorems

[LATEX]\bar{A}+\bar{B} = \overline{(A \times B)}[/LATEX]

[LATEX]\bar{A}\times\bar{B} = \overline{(A+B)}[/LATEX]

It may be helpful for implementation if you can only use a certain type of gate, for example... or just to make it more clear of how the function is working, perhaps.

It's useful to know if you're trying to simplify a boolean logic equation with nested group inversions.

They exist as simply a law of the equivalency.