BzzzzTTTT! The big cap has to be there to store energy between full wave rectified cycles from the bridge rectifier. At 60 Hz, the pulses out of the rectifier recharge said capacitor every 8.33ms, so all of the current delivered to the load COMEs out of capacitor until the next pulse.
Suppose that the power supply is trying to deliver 24V at 5A. The big capacitor will charge to about 1.2 times the rms voltage on the transformer secondary (1.2 because of transformer impedance and voltage drops across two silicon rectifiers in series). 1.2*24 = 28.8V. Since the supply is trying to deliver 24V to the load, that leaves only 4.8V of headroom.
Some of the headroom is used up by the dropout voltage of the regulator, which per the **broken link removed**. That leaves an allowable sag of 1.7V of the capacitor voltage during the 8msec before the next current pulse gets there.
So how big does the capacitor have to be to not let the voltage sag more than 1.7V with 5A of current discharging the capacitor? q=C*¦¤V=i*¦¤t. Rearranging, C=i*¦¤t/¦¤V= 5*0.008/1.7=0.024F (yes, that is Farads), or 24,000uF.
You can parallel as many caps as you want, but the total capacitance must be > than 24,000uF if you want your supply to deliver 5A at 24V. This supply will not deliver more than a few mA at 35V. btw- the voltage rating of your capacitor(s) should be ¡Ý 40Vw