Why do they have the P-channel FETs hooked up with the source towards the load? How are these devices working? I am more used to seeing things like Figure 7 for high-side P-channel power switches.
It's not working backwards. Current flows from Drain to Source. Since it's a p-channel MOSFET, VDG > -VT, and the MOS is in the low power dissapation region. The Sense pin of the IC keeps the FET in that region.
VDS is nearly zero, but that's because in a P-channel MOSFET, when VGS< VT and VDG > -VT, a strong inversion layer is formed between the drain and source, which is bidirectional.
EDIT: I edited all my conditions for low power dissapation. I get those confused easily.
The reason the source and drain is connected backward from what you might expect is so the parasitic MOSFET diode (which is connected anode to drain and cathode to source) does not conduct if the wall adapter voltage is significantly higher than the battery voltage, which would perform uncontrolled charging of the battery.