Is there a latch to replace this logic?

A

ACharnley

Member
I find myself doing this quite often and have occasionally wondered if there's a latch that can perform the same behaviour of the AND gate and SR.

SR - possible SR=1 violation
D - only actions on the clock
JR - don't want the toggle behaviour

The only thing I can think of is using 4 NAND gates to do the SR gate then using a pull-up on the second input of the S input (which is normally hidden) with a weak pull-up.
 

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There's not enough info to make sense of what you are asking.
 
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It sounds like you're looking for a latch with specific behavior. To replicate the functions of an SR latch, AND gate, and D latch, you can use a combination of NAND gates. This allows you to control the state changes. To prevent unwanted toggling, you can use a weak pull-up resistor on the second input of the S input. This helps maintain stability when not actively changing the state. It's a clever solution to achieve the desired functionality without violating the SR=1 condition or causing unintentional changes. Just ensure proper design and testing to make it work reliably in your circuit.

Download now to boost your creativity
 
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Some lazy sods on here not following through the simulation!

Yes, 4 NAND's appear to be the only way I can think off.

For explanation, the clock acts as a reset. If the comparator voltage is high when the clock comes in it SETS the RS. If the comparator voltage is low it immediately RESET's the RS (i.e async, unlike a D latch that waits on the clock).
 
Last edited:
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Not exactly true.
The 4013 dual D flip flop has an asynchronous Reset input.
 
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ACharnley said:
My understanding is using the SET/CLR at the same time as a single input is still classed as an invalid state (I did simulate with one in ltspice a few days ago).
Click to expand...

The is the truth table for the TI CD4013B



The last entry shows that if S and R are both high, both Q and Qbar are high.
They can be asserted independent of the clock.
 
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Be aware the LTspice default Dflop gives Q low and Q bar high when both the Preset and Clear inputs are simultaneously high.
 
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