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I can't post the DSP Processor as it's company internal (developed here).
However, it has indeed 3 registers.
Interrupt Mask Register, which each bit of it enables / disables specific interrupt.
Interrupt Latch Register, which each bit of it latches / not latches specific interrupt (What does it mean Latching an interrupt?)
Interrupt Pending Register, which each bit of it specifies if specific interrupt is pending (or active) / not active.
I assume that the Pending Register is for a case where more than one interrupt occurs at the same time (or lower priority interrupt occur while ISR or higher priority interrupt is active), right?
Latching an interrupt just means turning it on.. Some processors have software interrupts as well as the normal hardware interrupts....
Without a datasheet, I'm working blind..
The pic18's have three registers associated with an interrupt..
They have an "Enable" register ( Or they have a "latch" in a common register).
They have a flag ( status) register ( Or again a flag in a common register).
They have a priority register....
Seems similar to your works DSP..... But as I said... without any info... I'm guessing.
As I said several posts back!!! I do not know the hardware, the processor you are working on may have different levels of interrupt enabling....
If you google interrupt logic where Latching and masking are used, then you will see that some processors have several hardware interrupts... When an interrupt fires the relevant bit in the interrupt latch register is set. If the relevant bit in the interrupt mask register is unset, the interrupt is serviced, whereas, if the bit is set the interrupt is ignored ( masked ).
Your processor must have this kind of logic..... Most microprocessors behave the way I first described..
IE register ( interrupt enable ) This must resemble the mask register
IF register ( interrupt flag ) This must resemble the latch register
PR register ( priority )
I don't understand the need for three registers. The interrupt pending register appears to be the same as the pic's flags and therefore I don't understand the latch register. Can anyone explain why both latch and pending registers are required? Just curious.
I think it behaves like the H8 hitachi core... This had a weird interrupt set up as well. I would like to hear which core the processor is based on.... Even if you can't say the processors name, then surely you can tell us which architecture it has been built with?
Ian, it's built on Harvard Architecture, I'm not sure how it helps though, perhaps you meant something else?
As for the Pending Register,
Is the Pending Register checked every time the processor exists an ISR, in order to check whether another low-same priority interrupt occurred during the ISR?
I think you can look at it this way:
Interrupt Mask = what interrupts, will generate an interrupt request
Interrupt latch = You caught a fish. Generate an IRQ - service request.
So, you generally disable interrupts in the ISR or it's done automatically.
So, in this case, you CAN check for pending interrupts before you re-enable the the interrupts in the ISR (Return from Interrupt)
I think you can look at it this way:
Interrupt Mask = what interrupts, will generate an interrupt request
Interrupt latch = You caught a fish. Generate an IRQ - service request.
So, you generally disable interrupts in the ISR or it's done automatically.
Interrupt Pending:
So, in this case, you CAN check for pending interrupts before you re-enable the the interrupts in the ISR (Return from Interrupt)
Return from Interrupt with some pending would transfer those pending to interrupt latch and generate an interrupt.
Interrupts have to be automatically disabled in the ISR or the ISR will get interrupted and then things will get very messy.
The pending flags of all enabled interrupts have to be checked in the ISR and serviced which would include clearing the flag.
If a pending flag is set after the interrupt then a new interrupt will be generated. (triggered after being checked in ISR)
I still can't see any use for an interrupt latch register. Or maybe I'm missing something?
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