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Implementing ROM with Bus

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EngIntoHW

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Hey,

Could someone please explain how this bus is physically implemented?

In the below example, there's a 3-wire bus.

When, for example, address input is (0,0,0), then the output should be 1.
I don't understand how it works out.

Moreover, aren't these 8 AND gates supposed to be 'three-state' AND gates?
Meaning, each of them should have an Enable entry, that when zero, it outputs High-Z?

Thanks.

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hi,
The thick line represents 3 address wires.
Look at this image

EDIT:
I should add that the AND symbol is a complex AND function block and not just a 4 input AND.
You could image that the AND for ROM location '0' symbol represents say 3 inverters on the address line inputs which connect into a 4 input AND gate.
So when the 3 address lines are low and the Data bit is high the AND gate is enabled and the output onto the bus is '1'
 

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Hey, thanks.

I understand how it logically works, but I dont understand how it physically works.
Could you draw it in more details?

hi,
Did my EDIT help to explain it OK.?

EDIT
Added image
 

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Oh, so basically you implemented the ROM by a MUX, didn't you?

However, there's a conflict at the output, as I described in the attached image, isn't there?
 

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Oh, so basically you implemented the ROM by a MUX, didn't you?

However, there's a conflict at the output, as I described in the attached image, isn't there?

hi,
The AND gates would normally be open collector outputs and the bus line would have single pull up resistor to +V.
So conflict, as I stated in the drawing they are not the actual IC's.
 
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