Hey,
Could someone please explain how this bus is physically implemented?
In the below example, there's a 3-wire bus.
When, for example, address input is (0,0,0), then the output should be 1.
I don't understand how it works out.
Moreover, aren't these 8 AND gates supposed to be 'three-state' AND gates?
Meaning, each of them should have an Enable entry, that when zero, it outputs High-Z?
Thanks.
Could someone please explain how this bus is physically implemented?
In the below example, there's a 3-wire bus.
When, for example, address input is (0,0,0), then the output should be 1.
I don't understand how it works out.
Moreover, aren't these 8 AND gates supposed to be 'three-state' AND gates?
Meaning, each of them should have an Enable entry, that when zero, it outputs High-Z?
Thanks.
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