Impact of surrounding logic - causes

[HyperText]

Hi,

https://i.imgur.com/vsNsjOh.png

suppose that I have an FPGA, and, based on the image above, that I have a circuit that is synthesized on the bottom-left part of the FPGA (green box). Furthermore, suppose that I synthesized another circuit (red box) that surrounds the first. This last circuit is a high power demanding circuit, and it is basically a "disturbing circuit" (it is useless). I'd like to know if the red "disturbing" circuit, which is located very closely to the green one, might influence in some way the green circuit (I'm talking about ANY influence it might have, such as timings constraints, power instability, or whatever, and why).

I'm asking this question because from experiments on Xilinx Spartan-3E FPGA I noticed that the green circuit behaves differently depending on the position of the red one. Assuming that I have a ring oscillator (green box) and that I can measure its frequency, I noticed that when the red disturbing circuit is close to the ring oscillator circuit, the ring oscillator's frequency is slower than when the red circuit is far away.
I'd like to investigate the causes of this behavior. Any direction is welcomed

Thanks

 

[kubeek]

I think there are two major categories to this.
Standard clocked synchronous circuits should behave the same whatever you might do with the rest of the cells, as long as you abide timing constraints from the manufacturer.
Asynchronous circuits with feedback like ring oscillators, metastable random number generators etc., and especially those that are on the edge or straight violating timing constraints of the cells will likely be affected by anything that might be present in the rest of the chip, but also by any stray electric and magnetic fields and noise on power lines from other neighboring chips.

 

[MikeMl]

A ring oscillator is affected by anything in the vicinity, including the phase of the moon, the price of tea in China, the DOW, ...

I wouldn't loose sleep over its stability....