I2C pull-up...capacitor?!

[dknguyen]

Has anybody seen an I2C termination like this with a capacitor in series with the pull-up resistor? I've seen this on differential bus terminations to prevent reflections and the cap is there to reduce power consumption...but seeing as how in I2C and these are suppoed to be for pull-up it doesnt seem to make sense. Wouldn't it limit the slew rate?

 

[justDIY]

Analog seems to indicate the capacitors are used when the chip is employed for level shifting.

you (or someone) cropped the text explaining that diagram you've got

the next diagram shows a much more traditional configuration

https://www.analog.com/en/prod/0,2877,ADuM1250,00.html

 

[hjames]

The capacitors are mentioned in Table 2 of the data sheet where they specify the max operational frequency when the bus is loaded.

 

[Nigel Goodwin]

Has anybody seen an I2C termination like this with a capacitor in series with the pull-up resistor? I've seen this on differential bus terminations to prevent reflections and the cap is there to reduce power consumption...but seeing as how in I2C and these are suppoed to be for pull-up it doesnt seem to make sense. Wouldn't it limit the slew rate?

You're missing the point! - they aren't CAPACITORS they are CAPACITANCE, they represent the stray capacitance of the boad layout, and are essentially what the pullup resistors have to overcome - which is why they can't be too high a value. The diagram itself only shows them to explain the formulas that (presumably?) follow.

 

[dknguyen]

Oh, okay. THat makes sense. I thought they were discrete caps being added for some unknown purpose.

I guess that's why they were called CL rather than C1 and C2.

 

[Sceadwian]

The CL should describe it all, capacitive load.