I think I have a bug in my design. Please help

[Iawia]

Here is my schematic. sorry about the rough drawn. i figured it would be faster. I am having the output of the j/k flip flop to flip power off to most components when the counter reaches 5. but the counter continues counting and nothing turns off.

i have hooked up an alarm to trigger the 'J' value to high when the alarm goes off, thus i figured that when the k value is triggered by the counter turning '5', it would toggle the Q state, the components (except for the timer and the jk), then the alarm would run out, and it would be able to start all over again on the next alarm signal.

i noticed that the jk doesn't change until it is clocked, do you think this has anything to do with the positive edge components?

any help would be great. thanks!

 

[Reloadron]

What exactly are you doing with pins 3, 4, 5, & 6 of the 74161 counter? If you want to count to 5 and halt they need a binary 5.

Ron

 

[Iawia]

i grounded them to load zero. if i load a five. wont that start counting from 5? its an up counter.

 

[Iawia]

so what i did was 'look for 5', with the and gates, and try to change the state from j=1, k=0 --> j=1, k=1 which should toggle the power to off.

 

[crutschow]

...............i noticed that the jk doesn't change until it is clocked, do you think this has anything to do with the positive edge components?

That's proper operation. Flip-flops doesn't change states until they see a clock pulse. If you want it to change states with no clock, then you use the SET/RESET inputs.

 

[Mikebits]

You also need to be careful when mixing logic families.

**broken link removed**