(but you occasionally fail to capitalize "I"Marks256 said:Does anyone have a book that will explain, in great detail, how a computer works? When i say "how a computer works", i mean; the busses(and how they work), how addressing REALLYworks, the memory(DRAM, SRAM, and MCC's), what IRQ's Really are, what DMA and DMA Requests are. I would like to know. If anyone would care to leave a description, that would be great, but i would like a book. Actually, i would like it if someone would give me a taste, if you will, of what these things are, and how they function. Thanks!
Also, don't bother checking my spelling. I can guarantee that it is all right.
Thank goodness you ask for so little...
All busses are a collection of copper traces running point to point around the circuit board. The busses largely fall into three categories: data, address and control.
The first two are mostly involved with memory access. The address lines become selection controls that "pick" which memory cell (where a cell may be 1, 4, 8, or 16 bits wide) is being accessed within a RAM or ROM. Ocassionlly, the two lower address lines (A0 and A1) get used to select a register within some peripheral chip. As for control lines for RAM, these are minimally Read and Write. DRAM needs refresh management, and the Z80 has a REFRESH pin just for that. Which brings us to DMA...
DMA (Direct Memory Access) is a system of handshake signals that allow peripheral chips sole access to the memory for large memory data transfers. That is, a LOT of data gets read and written from RAM to some other place, like a hard drive, floppy or video board. This is usually accomplished with some peripheral chip used to manage devices like harddrives or intelligent busses, like SCSI. The PIC (AKA Peripheral Interface Chip, not the processor) sends out a bus request, which is just an input to the processor. Eventually the processor sees this and sends a signal back acknowledging the request. Sometimes the processor releases the address/data lines immediately, some times there's more handshaking. Eventually, the PIC has full uninterrupted control of the memory, and goes to town on it. The processor just twiddles its thumbs and marks time waiting for the PIC to finish (It either suspends its clock or does a continuous string of NOPs). When its job is done, the PIC starts a handshake in reverse that allows the processor to reclaim the memory and get on with its program.
As for the controls buss, this is typically read/write; interrupts; signals determining between access of code space and data space in memory (think 8080 and above); and DMA. The Z80 adds refresh control for Dynamic RAM (D-RAM).
Interrupts vary from chip to chip, but their purpose is typically to "interrupt" the processor in the middle of the present program and redirect it to another chunk of code. These interruptions are generally for handling time-critical (NOW, DAMMIT!!) jobs (the whisker sensor on your robot signals imminent collision with the wall, or the UART sees the START BIT come up during serial communications); or time-increment counts, where the processor is supposed to do some housekeeping chore like scan the keypad, then do debounce duty, or collect garbage and clean up variables storage. Most processors have a register dedicated to this task. There is a collection of 'bits'. One is a universal control bit. Make it high and all interrupts work; make it low and all interrupts are off. Then you have other bits that enable/disable the various interrupts available to the chip. These can be a pin that can never be ignored; another can be 'masked', so the processor can block it and do other work. Some external interrupts can be made to work on signal edges, or high levels, or low levels. Timed interrupts are 'slaved' to some internal clock, sometimes more than one.
Most embedded processors have only one address to go to at the start of an interrupt. The usual response to an interrupt is to
- suspend the present program
- disable all interrupts
- determine which interrupt was active
- process the appropriate code
- enable interrupts
- resume the interrupted program
More powerful processors may have 'vectored' interrupts, which are interrupts with a unique programmed address to jump to. They may also have 'prioritized' interrupts, which means they have a priority level assigned to them. So, if two interrupts come in at once, the one with the higher priority gets run first. If a lower interrupt is being run when a higher priority interrupt comes in, the lower one is suspended until the higher one is serviced to completion. Conversely, if a lower interrupt comes in while a higher one is being processed, the lower one is held off for later.
So, you want a simple description of how dynamic memory works? No such thing. If you want to twist your brain into a pretzel read a data sheet for a modern DRAM, end to end.
As for the book (I saved the best for last) I highly recommend
This $40 book has it all: starting with sub atomic principles, to electron flow theory, to semiconductors, to transistors, to electronic gates, to ICs, etc...
He eventually covers DC and AC theory; analog and digital circuits; the internals of RAM, ROM and processors; doing schematics, laying out boards, and electronics assembly; basic theory of computers; programming and all its considerations. He eventually teaches the basics of computer gaming. Its 800 pages of all-things-electronic.
BTW, if you go to the bottom of the web page, you'll see they allow you to download the table of contents, Chapter 1 (Basic electronics) and Chapter 11 (writing games? I'm foggy, it's been a while...). I hope you have fast DSL, both chapters are pretty big.
Let me put it to you this way: this book covers MORE than what I got in my two and a half years of college to get an AS in Electronics.
Nest ce pas, cheri?
Hope you found this useful,