How to Time delay/Phase delaying a TTL signal

[ronv]

OK. I thought maybe there was a reason it would not work for you. The circuit would be better if the resistor was a 100K pot and the capacitor 1/10 the size. It needs to be a Schmitt trigger inverter like the one shown.

 

[pavjayt]

OK. I thought maybe there was a reason it would not work for you. The circuit would be better if the resistor was a 100K pot and the capacitor 1/10 the size. It needs to be a Schmitt trigger inverter like the one shown.

Looking at your circuit, I noticed that I am already using a schmitt trigger MM74HC14M in the same circuit to invert the PLL output before feeding into LM556. I am not using all the circuits in it anyways, so I guess I can use one of those. I hope it wont be a problem for other circuits in that IC. Once I get this working, I am gonna move on to the LM556 part.

 

[ericgibbs]

Tried this and its working fine. The only think that I changed is to use 15V rather than 12V as I can see some distortion in the rising edge of the output at 12V. This can be used into my design, but I have access only to 5V on my digital board, are there any other variations of this using 5V or should it have to be above 12V?

hi,
You asked about a 5V option.

E.

 

[pavjayt]

hi,
You asked about a 5V option.

E.

Thanks Eric. I will try this one too.. I am just trying to decide which one to go for, analog or digital..... I will check which one is more reliable. One thing that I see in using analog is the sine amplitude reduces going through your circuit which is somewhat a problem for us as our sine amplitude starts from 0 and we would like to lock on it as soon as the amplitude of it changes. I hope it wont be a big problem for us, will see..

 

[pavjayt]

OK. I thought maybe there was a reason it would not work for you. The circuit would be better if the resistor was a 100K pot and the capacitor 1/10 the size. It needs to be a Schmitt trigger inverter like the one shown.

I tried your circuit with a 150K pot and 220pF cap and the results are as shown in the video file attached.

I am going through two inverters.

Any suggestions on how to reduce the jitter. I need atleast 1/4 cycle of adjustment.

thanks

 

[ronv]

Hmmm. Might try a larger cap and a smaller pot. Also a little decoupling cap on the +5 to ground might help. Say a 0.1 ceramic.

Is the integrated waveform jittery or is the amplitude changing?

 

[pavjayt]

Hmmm. Might try a larger cap and a smaller pot. Also a little decoupling cap on the +5 to ground might help. Say a 0.1 ceramic.

Is the integrated waveform jittery or is the amplitude changing?

I got it working with a 220p cap and 150K pot and Vcc decoupling. Its still jittery if I go more offset.

Both designs are working, thanks. I will use digital for now after the PLL and try to use analog design once I get the PLL working with sine wave so that I can use this offset design before the PLL.

 

[pavjayt]

Later on in the circuit I am using 556 dual timer to delay the square wave and also to change the duty cycle of it. As I said earlier, I was not able to adjust much at all with LM556CMX IC nor LM556CN (in which case I don't see any output at all). Then to my luck, I found ALD7556 IC and thought I would give it a try. This worked great. Same circuit on the breadboard, just changing the IC. Do you guys have any ideas why it would be like that?

 

[ericgibbs]

hi,
The ALD7556 is CMOS technology, the others LM556 are TTL technology.

The CMOS timers introduce less 'noise' into the power lines than the TTL versions
E.

 

[pavjayt]

hi,
The ALD7556 is CMOS technology, the others LM556 are TTL technology.

The CMOS timers introduce less 'noise' into the power lines than the TTL versions
E.

Thanks for that info. LM556 is working with TTL trigger, but narrow adjustment range while ALD7556 has more range and stability too even with a TTL trigger. The input for my LM556 is the output from a 74HC14 hex inverter whose input is the output of a 4046 PLL. I guess I can safely use ALD7556 inplace of my LM556.

 

[pavjayt]

74HC4046 output jitter

I noticed something new in my PLL circuit that the output has jitter. The exact same circuit works without phase jitter on another PCB with the same PLL design. Any suggestions?

The input itself is very stable at 15.2Khz as you can see in the picture on channel 4.