You can either stop Timer0 entirely by setting bit TR0 = 0, or you can disable Timer0 interrupts by setting bit ET0 = 0. You decide which method suits your requirements.
But it's only an indication, not 100%, there's nothing to stop you having a *.h file called that for a PIC compiler. But really it's a very sloppy question not to mention what processor you're asking about, expecting people to be detectives and work it out!.
The names of the Special Function Registers(SFR) and the bits that go with them pretty much indicates the target of this particular C program. We didn't start doing this stuff yesterday, and we might be expected to recognize at least the family if not the specific variant that was being used from register names alone.
First review your code for some typo's.
Description stated port 1.0
In code I see P0_1, P0_0 and again P1.0 in comment. So what will it be?
Timer 0 in mode 1 is a 16 bit timer. Each time the count rolls over from all 1s to all 0s it sets the interrupt flag. Tell me how you get a 1Khz timer (your comment) with a value of FEFF! With a 12MHz osc I got 12MHz/12 * (FFFF - FEFF) = 275µs = 3.6kHz
Your code: while(TF0==0); // Timer0 Over Flow flag=0 without parenthesis, is that normal? I'm not a C guy Always assembler
And: why using TF0 anyway? It's set by hardware on timer overflow and cleared by hardware when the ISR is serviced. Since you use the ISR, why using TF0?
You need to reload the timer at each ISR. These are the first asm lines I use in my ISR
Code:
;------------------------------------------------------------------------------
RSEG TMR0_Code
Timer_0:
mov th0,#High Time_0 ;Restart timer
mov tl0,#Low Time_0
push acc ;Save registers used in ISR
push b
push dph
push dpl
push psw