Normally the are queued! The interrupts cannot read the interrupt flags until the interrupt is serviced... Once the interrupt is done, the second flag will be dealt with..
On some micro's there is a priority... Interrupts can be interrupted by a higher level interrupt... Under these conditions careful interrupt software programming is required..
The 8052 series has several interrupts... The mid range pic has only one, the enhanced has two.
Some have a whole host in hardware AND software interrupts...
Which processor are you looking at??