How to get full speed from MSSP port?

[Mr RB]

Darn this has been biting me for about 20 minutes, but I have never really used the MSSP port for high speed stuff so I'm probably missing some little trick or something.

I have a PIC 18F452 running 10MHz xtal PLL so it's Fosc is 40Mhz and PIC is 10 MIPS.
The MSSP port is set for fosc/4 so it SHOULD give me a maximum data out bitrate of 10 Mbit/sec, that is even quoted in the datasheet.

But the very best I can get is 8.8 Mbit per second, it seems to always be using 9 clock periods to send 8 bits!!

I have stripped the code down to the simplest ASM and counted cycles etc etc, there's no way i can get this thing running at the quoted maximum 8 bits per 8 PIC cycles.

This is an example of the code I have been testing (although I have tried umpeen variations in testing);

SSPSTAT = 0;
SSPCON1 = 0b00100000;  // SSP on, fosc/4 (10 Mbit/sec)

blah:     // 8 PIC cy loop
  i = SSPBUF;    // 2 cy
  SSPBUF = 0b11110000;  // 2 cy
  asm nop;    // 1 cy
  SSPCON1.WCOL = 0;    // 1 cy
  goto blah;  // 2 cy

I have tried re-arranging the order, adding nops removing nops etc but there seems no way it will send 8 bits in 8 PIC cycles (as claimed in the datasheet).
The output on SDO (RC5) should read 10 mips/8 or 125000 Hz, but it will only give me 111111 Hz which is 8/9ths of the correct speed.

I don't need to receive only to send data at 10 Mbit/sec.

So rather than pull my hair out for another 20 mins I thought of asking the people who know the MSSP port much better than I do.

 

[Pommie]

I vaguely remember this coming up before and the conclusion was that it was an bug in the silicon. From memory 9 data bits were sent but only 8 clock pulses and so it worked as intended but with a bit delay between bytes. Is this what you are seeing? It may be specific to that chip, can you try a different one?

Mike.

 

[Mr RB]

Thanks for the quick reply Pommie. I might have to drag it out to the workshop and get the CRO on it.

Currently I have only tested on 18F452, but I have some other 18F PLL PICs that I can try later.

I was just reading the datasheet again, maybe it's also a problem with CKE (selects clock on rising/falling edge)...

 

[Mr RB]

Well there is no good news from my end. I hooked it up to the CRO and did over an hour of testing, every possible MSSP register setup permutation and change in code.

I only tested the 18F452 but with that MSSP module and running at 10MIPS it always takes minimum 9 PIC instructions to send the 8 SPI bits. Trying to do it in 8 PIC instructions just results in a MSSP error (buffer overwrite?) that drops it to half speed.

Sorry Pommie I can't say for the other PICs (so I couldn't test your suggestion) but for this one anyway it's just not possible to get the continuous 10 Mbit/sec quoted in the datasheet.

 

[Oznog]

Check the Errata sheet for your 452. You will want to find the silicon revision number to figure out which errata sheet applies, which should come up if you have a good programmer. The errata sheet often has suggested "workarounds".

452 is an obsolete chip, superseded by the 4520.

 

[Mr RB]

Thanks Oznog I just downloaded the latest errata for the 18F452. There is a MSSP problem mentioned but it is not related.

It seems this speed issue is one of those "undocumented features". The MSSP is specced at 10 Mbit/sec, which technically it is (for each actual data bit) but there is a unavoidable 1 tick delay involved in loading/sending every 8 bits so it takes 9 PIC clocks to send 8 data bits, so real data rate is 10 Mbit/sec /9*8 or 8.88Mbit/sec.