;
; DDS Frequency (Fdds) = 65536 Hz (Fosc = 8.388608 MHz)
; Resolution (Fres) = Fdds / 2^16 = 1.0 Hz (16 bit accumulators)
; 1.0-KHz phase offset = 1000 / Fres = 1000
; 2.1-KHz phase offset = 2100 / Fres = 2100
;
radix dec
dds1
clrf shadow ; |B0
movlw low(2100) ; phase offset for 2100-Hz |B0
addwf accum1+0,F ; accum1 += phase1 |B0
movlw high(2100) ; |B0
skpnc ; |B0
addlw 1 ; |B0
addwf accum1+1,F ; |B0
movlw 128 ; 64=25%, 128=50%, 192=75% |B0
addwf accum1+1,W ; (pulse width) |B0
rlf shadow,F ; collect the Carry bit |B0
dds2
movlw low(1000) ; phase offset for 1000 Hz |B0
addwf accum2+0,F ; accum2 += phase2 |B0
movlw high(1000) ; |B0
skpnc ; |B0
addlw 1 ; |B0
addwf accum2+1,F ; |B0
movlw 128 ; 64=25%, 128=50%, 192=75% |B0
addwf accum2+1,W ; (pulse width) |B0
rlf shadow,W ; collect the Carry bit |B0
movwf GPIO ; update GP1 & GP0 outputs |B0
DelayCy(32-22) ; 32 cycle DDS loop |B0
goto dds1 ; |B0
;