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...So, may I know how to start with the nanosecond measurement?
Spend about $10,000 on a sampling digital oscilloscope that can sample at a rate of 1GHz (1 ns resolution)
Actually you can do this for less than $1, of course it won't be as precise as a GHz scope, but it can work. Look up how a PLL phase detector is implemented...
To measure the delay of circuit X, send a clock signal of suitable frequency into it, and use a fast 74AHC XOR gate to compute the (input of X) XOR (output of X). RC filter the output. The average voltage is proportional to the time delay modulo clock period. Pay attention to layout.
And what if outputX is a complex function of inputX, like a counter.
Spend about $10,000 on a sampling digital oscilloscope that can sample at a rate of 1GHz (1 ns resolution)
And what if outputX is a complex function of inputX, like a counter. There is no (useful) predictable, correlation between them. Your idea would work to measure a delay line, but not for measuring the delay through multilevel combinatorial logic, let alone sequential logic.
Hi!
Thanks for the reply. can you send me the schematic diagram about ur suggestion as the quote above?
like i said, 2 programmable delay lines will allow you two determine the delay through the logic
After I read through the datasheet of DS1124, I am curious about the pin IN and OUT of the chip. How it related to the 2 programmable delay lines? How to use DS1124 to measurement the chip delay?