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how to design JFET amplifer..?

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zack88

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i have prob wif this question. can refer to this web http://www.answerbag.com/q_view/484268for the full question. if u need more info, just post reply here. :) thank you very much

Design:

a Junction Field Effect Transistor (JFET) amplifier that meets the required specifications. Required Specifications: Voltage Gain: > 10 Input Resistance: >100 k? Load Resistance: 100 k? Supply Voltage: 30 V Output Voltage Swing: > 1


 
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ericgibbs

Well-Known Member
Most Helpful Member

audioguru

Well-Known Member
Most Helpful Member
I will be the simplest Jfet amplifier circuit I have ever seen. Very, very simple. Extremely simple.
Didn't your teacher teach about it?
Doesn't the text book explain it?
Doesn't Google explain it?
Maybe little school kids should be banned from here.
 

ericgibbs

Well-Known Member
Most Helpful Member
hi zack,
When I said post the details, thats to the Thread not as PM to me..:D

Copy of your PM.
JFET DESIGN
Project Description:
Design a Junction Field Effect Transistor (JFET) amplifier that meets the required
specifications. Heavy emphasis is placed on the theory and comparison with simulation
results.
Required Specifications:
Voltage Gain: > 10
Input Resistance: >100 kΩ
Load Resistance: 100 kΩ
Supply Voltage: 30 V
Output Voltage Swing: > 10 V peak-to-peak
Operating Frequency: 1 kHz
Design Procedure:
1. Select a suitable JFET.
2. Design the amplifier by hand. Using the datasheet values,
(i) Choose a value for ID(max) for the case of IDSS(max) and VP(max)
(ii) For the case of IDSS(min) and VP(min), choose ID(min) to be 80% - 90% of
ID(max)
(iii) Perform hand-analysis to find the required biasing resistors and coupling/
bypass capacitors
(iv) Analyse the voltage gain and output voltage swing for the two extreme
cases (IDSS(max) - VP(max), and IDSS(min) - VP(min)). If the required
specifications cannot be met, go back to step (i), choose a new value for
ID(max) and repeat the design process.
3. Using PSPICE software, simulate the amplifier performance. Make computer printout of the schematic diagram, with DC voltages and currents at every node indicated. Also produce a plot of input and output voltage waveforms at 1 kHz, with the amplitude of the sinewave signal source set to a value that gives maximum voltage swing at the load resistor without noticeable distortion.
4. Compare the hand analysis and the simulated results. The PSPICE transistor model uses fixed values of IDSS and VP. The simulation results will not match the hand analysis but they should fall in between the two extreme cases.

Note:
1. DC voltage and current values can be obtained by enabling bias voltage display and bias current display in the schematic window.
2. By checking "Detailed Bias Pt." option in the transient analysis setup, gm can be viewed in the simulation output file (*.OUT).
3. Av can be obtained by dividing output voltage at RL by its corresponding input voltage Vi​
 

Hwai

New Member
Excuse me, could anyone shows me how to solve the question posted as I'm run out of ideas? Thks

Please start a New Thread for your project.

Moderation:E.
 
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audioguru

Well-Known Member
Most Helpful Member
Excuse me, could anyone shows me how to solve the question posted as I'm run out of ideas?
This is Zack's thread for his homework, not yours.
We want Zack to post his design then we will help him if he has something wrong.
Then we want to see your design and we will help you if you have something wrong.
 
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